[PATCH] D156390: [SDAG][RISCV] Avoid expanding is-power-of-2 pattern on riscv32/64 with zbb

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/rvv/ctpop-sdnode.ll:860
 }
+
+define <vscale x 16 x i1> @ctpop_nxv16i32_ult_two(<vscale x 16 x i32> %va) {
----------------
dtcxzyw wrote:
> craig.topper wrote:
> > These tests already pass.
> > The vector part of this isn't tested.
> 
> Should I remove these useless tests? We always emit `vcpop` for the vector part.
> 
You can keep them. Just be clear in the description that they already pass.

We do need additional tests for fixed vector without "vscale x". I bet they don't pass without this patch.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156390/new/

https://reviews.llvm.org/D156390