[PATCH] D158839: [SDAG] Add SimplifyDemandedBits support for ISD::SPLAT_VECTOR

[Luke Lau via Phabricator via llvm-commits]

luke added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1162
+
+    Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth);
+    break;
----------------
RKSimon wrote:
> Do you need this or can you just set it to KnownScl (with suitable truncation)?
I think computeKnownBits does exactly that, will replace it


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158839/new/

https://reviews.llvm.org/D158839