[PATCH] D158824: [RISCV][MC] MC layer support for xcvmem and xcvelw extensions

[Shao-Ce SUN via Phabricator via llvm-commits]

sunshaoce added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVFeatures.td:818
+   : SubtargetFeature<"xcvelw", "HasVendorXCVelw", "true",
+                      "'XCVelw' (Event Load Word)">;
+def HasVendorXCVelw
----------------
"'XCVelw' (CORE-V Event Load Word)"


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158824/new/

https://reviews.llvm.org/D158824