[PATCH] D158824: [RISCV][MC] MC layer support for xcvmem and xcvelw extensions

[Liao Chunyu via Phabricator via llvm-commits]

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This commit is part of a patch-set to upstream the 7 vendor specific extensions of CV32E40P.
Several other extensions have been merged.
Spec:
https://github.com/openhwgroup/cv32e40p/blob/master/docs/source/instruction_set_extensions.rst


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D158824

Files:
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/corev/XCVelw-invalid.s
  llvm/test/MC/RISCV/corev/XCVelw-valid.s
  llvm/test/MC/RISCV/corev/XCVmem-invalid.s
  llvm/test/MC/RISCV/corev/XCVmem-valid.s

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