[PATCH] D158759: [RISCV] Add a pass to rewrite rd to x0 for AMO instrs whose return values are unused
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 24 11:46:09 PDT 2023
craig.topper added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVTargetMachine.cpp:398
insertPass(&DetectDeadLanesID, &RISCVInitUndefID);
-
+ insertPass(&DetectDeadLanesID, &RISCVOptAMOInstrsID);
TargetPassConfig::addOptimizedRegAlloc();
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Does this depend on DetectDeadLanes?
AArch64 has a pass called AArch64DeadRegisterDefinitions that is inserted in addPreRegAlloc.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D158759/new/
https://reviews.llvm.org/D158759
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