[PATCH] D158053: [Legalizer] Expand fmaximum and fminimum

[Qiu Chaofan via Phabricator via llvm-commits]

qiucf added a subscriber: SixWeining.
qiucf added a comment.

In D158053#4607756 <https://reviews.llvm.org/D158053#4607756>, @arsenm wrote:

> In D158053#4605852 <https://reviews.llvm.org/D158053#4605852>, @qiucf wrote:
>
>> In D158053#4598440 <https://reviews.llvm.org/D158053#4598440>, @arsenm wrote:
>>
>>> I think we should either define the existing FMINNUM_IEEE/FMAXNUM_IEEE to have the correct IEEE 2019 signed zero ordering (I can't name a target that doesn't have this behavior), or we have to add a pair of DAG nodes that do
>>
>> Some targets have instructions legal for `fminnum_ieee`. It's better to add new one.
>
> I thought AMDGPU was the only one using it, but I see PPC and Loongarch have started. AMDGPU definitely has the correct signed zero behavior, so do the other 2?

PowerPC VSX max/min instruction (1) respects zero sign ordering; (2) `max(QNaN, non-NaN) = non-NaN`; (3) `max(SNaN, *) = QNaN`, so it matches `fmaximum_ieee` semantics. (Page 735 Power ISA 3.1 <https://wiki.raptorcs.com/w/images/f/f5/PowerISA_public.v3.1.pdf>).

LoongArch ISA <https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#_fmaxminsd> says '//the operation of these two instructions follows the specification of maxNum(x,y) operation in the IEEE 754-2008 standard//', so I think it is also right. (CC @SixWeining )

It seems no way to get `fmaximum_ieee/fminimum_ieee` through IR?


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