[PATCH] D155995: [AMDGPU]: Allow combining into v_dot4

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIISelLowering.cpp:12457
+                     unsigned ChainLength) {
+  for (auto &Entry : Srcs) {
+    Entry.second = Entry.second >> ((4 - ChainLength) * 8);
----------------
auto &[Something, Mask] : ?


================
Comment at: llvm/lib/Target/AMDGPU/SIISelLowering.cpp:12464-12480
+static unsigned getMulOpcode(const SDValue Op) {
+  auto Opcode = Op.getOpcode();
+  if (Opcode == ISD::INTRINSIC_WO_CHAIN) {
+    auto IID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
+    if (IID == Intrinsic::amdgcn_mul_i24)
+      return AMDGPUISD::MUL_I24;
+    if (IID == Intrinsic::amdgcn_mul_u24)
----------------
I thought we combined the mul24 intrinsics to the nodes specifically so you don't need to do this


================
Comment at: llvm/lib/Target/AMDGPU/SIISelLowering.cpp:12634-12635
+    SDValue IID =
+        IsSigned ? DAG.getTargetConstant(Intrinsic::amdgcn_sdot4, SL, MVT::i64)
+                 : DAG.getTargetConstant(Intrinsic::amdgcn_udot4, SL, MVT::i64);
+
----------------
DAG.getTargetConstant(IsSigned ? Intrinsic::amdgcn_sdot4 : Intrinsic::amdgcn_udot4, SL, MVT::i32)


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155995/new/

https://reviews.llvm.org/D155995