[PATCH] D158366: [DAG] replaceStoreOfInsertLoad - don't fold if the inserted element is implicity truncated
Simon Pilgrim via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Sun Aug 20 08:06:18 PDT 2023
RKSimon updated this revision to Diff 551839.
RKSimon added a comment.
fix dumb typo
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D158366/new/
https://reviews.llvm.org/D158366
Files:
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/test/CodeGen/X86/pr64655.ll
Index: llvm/test/CodeGen/X86/pr64655.ll
===================================================================
--- llvm/test/CodeGen/X86/pr64655.ll
+++ llvm/test/CodeGen/X86/pr64655.ll
@@ -41,7 +41,16 @@
;
; AVX512-LABEL: f:
; AVX512: # %bb.0:
-; AVX512-NEXT: movb $1, 1(%rdi)
+; AVX512-NEXT: kmovb (%rdi), %k0
+; AVX512-NEXT: movb $-3, %al
+; AVX512-NEXT: kmovd %eax, %k1
+; AVX512-NEXT: kandb %k1, %k0, %k0
+; AVX512-NEXT: movb $1, %al
+; AVX512-NEXT: kmovd %eax, %k1
+; AVX512-NEXT: kshiftlb $7, %k1, %k1
+; AVX512-NEXT: kshiftrb $6, %k1, %k1
+; AVX512-NEXT: korb %k1, %k0, %k0
+; AVX512-NEXT: kmovb %k0, (%rdi)
; AVX512-NEXT: retq
%2 = load <8 x i1>, ptr %0
%3 = insertelement <8 x i1> %2, i1 true, i32 1
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -20508,9 +20508,11 @@
SDValue Elt = Value.getOperand(1);
SDValue Idx = Value.getOperand(2);
- // If the element isn't byte sized then we can't compute an offset
+ // If the element isn't byte sized or is implicitly truncated then we can't
+ // compute an offset.
EVT EltVT = Elt.getValueType();
- if (!EltVT.isByteSized())
+ if (!EltVT.isByteSized() ||
+ EltVT != Value.getOperand(0).getValueType().getVectorElementType())
return SDValue();
auto *Ld = dyn_cast<LoadSDNode>(Value.getOperand(0));
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