[PATCH] D158163: [RISCV] Narrow types of index operand matched pattern (shl_vl (zext_vl), C)

[Yeting Kuo via Phabricator via llvm-commits]

fakepaper56 added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:11229
+  // just use the input to the extract.
+  if (N1.getOpcode() == ISD::INSERT_SUBVECTOR) {
+    SDValue N10 = N1.getOperand(0);
----------------
liaolucy wrote:
> fakepaper56 wrote:
> > The combine code exists in `DAGCombiner::visitINSERT_SUBVECTOR`. Why do we need this here?
> an example:
> ```
> 
> Legalized selection DAG: %bb.0 'vpscatter_baseidx_zext_v8i8_v8i16:'
> SelectionDAG has 26 nodes:
>   t0: ch,glue = EntryToken
>   t32: nxv4i1 = RISCVISD::VMSET_VL Constant:i64<8>
>       t2: nxv4i16,ch = CopyFromReg t0, Register:nxv4i16 %0
>       t6: i64,ch = CopyFromReg t0, Register:i64 %1
>           t8: nxv4i8,ch = CopyFromReg t0, Register:nxv4i8 %2
>         t33: nxv4i64 = RISCVISD::VZEXT_VL t8, t32, Constant:i64<8>
>             t43: nxv4i64 = RISCVISD::VMV_V_X_VL undef:nxv4i64, Constant:i64<1>, Constant:i64<8>
>           t44: v8i64 = extract_subvector t43, Constant:i64<0>
>         t36: nxv4i64 = insert_subvector undef:nxv4i64, t44, Constant:i64<0>
>       t37: nxv4i64 = RISCVISD::SHL_VL t33, t36, undef:nxv4i64, t32, Constant:i64<8>
>       t11: nxv4i1,ch = CopyFromReg t0, Register:nxv4i1 %3
>         t14: i64,ch = CopyFromReg t0, Register:i64 %4
>       t16: i64 = AssertZext t14, ValueType:ch:i32
>     t42: ch = llvm.riscv.vsoxei.mask<(store unknown-size, align 2)> t0, TargetConstant:i64<8783>, t2, t6, t37, t11, t16
>   t28: ch = RISCVISD::RET_GLUE t42
> ```
> visitINSERT_SUBVECTOR is executed after this code, and block this optimization, so add these here.
> 
Thank you for your elaboration. I misunderstood the order of legalization.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158163/new/

https://reviews.llvm.org/D158163