[PATCH] D158163: [RISCV] Narrow types of index operand matched pattern (shl_vl (zext_vl), C)

[Yeting Kuo via Phabricator via llvm-commits]

fakepaper56 added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:11201
+bool isVMV_V_X_VLOfConstant(SDValue N, APInt &SplatVal) {
+  auto *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
+  if (C && N.getOpcode() == RISCVISD::VMV_V_X_VL) {
----------------
fakepaper56 wrote:
> It may cause assertion error when N has exactly one operand. 
I think you could write to
```
if (N.getOpcode() == RISCVISD::VMV_V_X_VL && isa<ConstantSDNode>(N->getOperand(1))) {
  SplatVal = N->getConstantOperandVal(1);
  return true;
}
``` 


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158163/new/

https://reviews.llvm.org/D158163