[PATCH] D157231: [SPARC][IAS] Add definitions for v9 State Registers

[Sergei Barannikov via Phabricator via llvm-commits]

barannikov88 added inline comments.


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Comment at: llvm/test/MC/Sparc/sparcv9-instructions.s:425
         ! V9: rd %pc, %o7               ! encoding: [0x9f,0x41,0x40,0x00]
         rd %pc, %o7
+        ! V9: rd %asi, %g1              ! encoding: [0x83,0x40,0xc0,0x00]
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koakuma wrote:
> barannikov88 wrote:
> > barannikov88 wrote:
> > > koakuma wrote:
> > > > barannikov88 wrote:
> > > > > IIUC all of these should complain about missing feature on V8. This can probably be done by adding some checks to validateTargetOperandClass or checkTargetMatchPredicate.
> > > > > 
> > > > How do I do this? Seems like in both functions I can only get the raw register number, I don't know how to recover the textual name (e.g whether it was originally referred to as %asi or %asr3)...
> > > validateTargetOperandClass allows you to examine whatever you stored in SparcOperand. If the spelling is important, you can store that information there, see e.g. RegOp::RegisterKind.
> > > The method should probably return Match_MissingFeature on failure.
> > > 
> > There may be other solutions, but I'm not sure I understand the issue.
> > 
> The problem is that, for example, the two textual forms are encoded the same:
> ```
> rd %asr5, %i0
> rd %pc, %i0
> ```
> But the latter form is only allowed when targeting V9, so I want to be able to recover the textual names instead of just the register number?
> For comparison, GCC does disallow the %pc form when targeting non-V9 subarches (Sun's does not support targeting non-V9s in the first place).
When parsing a register (SparcAsmParser::matchRegisterName) you can record the spelling (as a flag/enum or string), pass it to SparcOperand::CreateReg and store in SparcOperand::RegOp, similar to RegisterKind. Then you can override checkEarlyTargetMatchPredicate where you can examine the spelling and filter out those that are invalid for the instruction and processor mode depending on the instruction opcode. If the opcode is not important (e.g. %pc is invalid for all instructions in V8 mode), then you can do the same in validateTargetOperandClass.

The tests should cover all register number/ register spelling / processor mode combinations, and there should also be disassembler tests for all combinations of registers / instructions / processor mode.

If all that sounds too difficult, can you add a TODO with the desired behavior somehwere? I.e. which processor mode / instruction allows which spelling?



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  https://reviews.llvm.org/D157231/new/

https://reviews.llvm.org/D157231