[PATCH] D157231: [SPARC][IAS] Add definitions for v9 State Registers

[Koakuma via Phabricator via llvm-commits]

koakuma marked 2 inline comments as not done.
koakuma added inline comments.


================
Comment at: llvm/lib/Target/Sparc/SparcRegisterInfo.td:135
+def GL         : SparcCtrlReg<16, "GL">;
+def VER        : SparcCtrlReg<31, "VER">;
 
----------------
barannikov88 wrote:
> koakuma wrote:
> > barannikov88 wrote:
> > > It looks like these registers are actually aliases to %asrXX (or vice versa). They should use the corresponding functionality instead of being redefined.
> > > See RegAltNameIndex in Target.td and how other targets use it.
> > > 
> > The privileged ones are on a separate register file from the ASRs, so those need to be defined separately.
> > 
> > The unprivileged ones can be merged with the ASRs, however, I have a question about the handling of %tick/%asr4.
> > The same register can be viewed through nonprivileged (rd %tick/rd %asr4) or privileged (rdpr %tick) instructions, however, since the two are modeled using different objects, it is quite difficult to make it usable by both instructions.
> > Currently I am special casing it so that privileged TICK can also be read by `rd`. Is there any better way to do this or will this do for now?
> I can't suggest anything better. Do other assemblers accept %asr1-6? The manual says there are only %asr7-31 (with 7-15 reserved for future use).
> Note that adding TICK to ASRRegs allows it to be used in `wr` instruction, which isn't allowed by the manual (A.63 Write State Register).
> 
GCC's assembler, at least, accepts the names %asr1-6 with both `rd` and `wr`, including the forbidden `wr` to %asr4/TICK and %asr5/PC.
Sun's, on the other hand, accepts the names %asr1-6 when using it with `rd`, but forbids it with `wr`.


================
Comment at: llvm/test/MC/Sparc/sparcv9-instructions.s:425
         ! V9: rd %pc, %o7               ! encoding: [0x9f,0x41,0x40,0x00]
         rd %pc, %o7
+        ! V9: rd %asi, %g1              ! encoding: [0x83,0x40,0xc0,0x00]
----------------
barannikov88 wrote:
> barannikov88 wrote:
> > koakuma wrote:
> > > barannikov88 wrote:
> > > > IIUC all of these should complain about missing feature on V8. This can probably be done by adding some checks to validateTargetOperandClass or checkTargetMatchPredicate.
> > > > 
> > > How do I do this? Seems like in both functions I can only get the raw register number, I don't know how to recover the textual name (e.g whether it was originally referred to as %asi or %asr3)...
> > validateTargetOperandClass allows you to examine whatever you stored in SparcOperand. If the spelling is important, you can store that information there, see e.g. RegOp::RegisterKind.
> > The method should probably return Match_MissingFeature on failure.
> > 
> There may be other solutions, but I'm not sure I understand the issue.
> 
The problem is that, for example, the two textual forms are encoded the same:
```
rd %asr5, %i0
rd %pc, %i0
```
But the latter form is only allowed when targeting V9, so I want to be able to recover the textual names instead of just the register number?
For comparison, GCC does disallow the %pc form when targeting non-V9 subarches (Sun's does not support targeting non-V9s in the first place).


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  https://reviews.llvm.org/D157231/new/

https://reviews.llvm.org/D157231