[llvm] 1b95661 - [AArch64] Regenerate sve-fixed-length-fp-minmax.ll
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Sun Aug 20 03:46:52 PDT 2023
Author: Simon Pilgrim
Date: 2023-08-20T11:46:44+01:00
New Revision: 1b956616162f2788673d18432cb538365646fdde
URL: https://github.com/llvm/llvm-project/commit/1b956616162f2788673d18432cb538365646fdde
DIFF: https://github.com/llvm/llvm-project/commit/1b956616162f2788673d18432cb538365646fdde.diff
LOG: [AArch64] Regenerate sve-fixed-length-fp-minmax.ll
Should remove the D158053 diffs
Added:
Modified:
llvm/test/CodeGen/AArch64/sve-fixed-length-fp-minmax.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-minmax.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-minmax.ll
index 1714be3f59a490..a736fdf8d5bf7b 100644
--- a/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-minmax.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-minmax.ll
@@ -48,7 +48,7 @@ define void @fmaxnm_v16f16(ptr %a, ptr %b) vscale_range(2,0) #0 {
define void @fmaxnm_v32f16(ptr %a, ptr %b) #0 {
; VBITS_EQ_256-LABEL: fmaxnm_v32f16:
; VBITS_EQ_256: // %bb.0:
-; VBITS_EQ_256-NEXT: mov x8, #16
+; VBITS_EQ_256-NEXT: mov x8, #16 // =0x10
; VBITS_EQ_256-NEXT: ptrue p0.h, vl16
; VBITS_EQ_256-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]
; VBITS_EQ_256-NEXT: ld1h { z1.h }, p0/z, [x0]
@@ -146,7 +146,7 @@ define void @fmaxnm_v8f32(ptr %a, ptr %b) vscale_range(2,0) #0 {
define void @fmaxnm_v16f32(ptr %a, ptr %b) #0 {
; VBITS_EQ_256-LABEL: fmaxnm_v16f32:
; VBITS_EQ_256: // %bb.0:
-; VBITS_EQ_256-NEXT: mov x8, #8
+; VBITS_EQ_256-NEXT: mov x8, #8 // =0x8
; VBITS_EQ_256-NEXT: ptrue p0.s, vl8
; VBITS_EQ_256-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]
; VBITS_EQ_256-NEXT: ld1w { z1.s }, p0/z, [x0]
@@ -244,7 +244,7 @@ define void @fmaxnm_v4f64(ptr %a, ptr %b) vscale_range(2,0) #0 {
define void @fmaxnm_v8f64(ptr %a, ptr %b) #0 {
; VBITS_EQ_256-LABEL: fmaxnm_v8f64:
; VBITS_EQ_256: // %bb.0:
-; VBITS_EQ_256-NEXT: mov x8, #4
+; VBITS_EQ_256-NEXT: mov x8, #4 // =0x4
; VBITS_EQ_256-NEXT: ptrue p0.d, vl4
; VBITS_EQ_256-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]
; VBITS_EQ_256-NEXT: ld1d { z1.d }, p0/z, [x0]
@@ -346,7 +346,7 @@ define void @fminnm_v16f16(ptr %a, ptr %b) vscale_range(2,0) #0 {
define void @fminnm_v32f16(ptr %a, ptr %b) #0 {
; VBITS_EQ_256-LABEL: fminnm_v32f16:
; VBITS_EQ_256: // %bb.0:
-; VBITS_EQ_256-NEXT: mov x8, #16
+; VBITS_EQ_256-NEXT: mov x8, #16 // =0x10
; VBITS_EQ_256-NEXT: ptrue p0.h, vl16
; VBITS_EQ_256-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]
; VBITS_EQ_256-NEXT: ld1h { z1.h }, p0/z, [x0]
@@ -444,7 +444,7 @@ define void @fminnm_v8f32(ptr %a, ptr %b) vscale_range(2,0) #0 {
define void @fminnm_v16f32(ptr %a, ptr %b) #0 {
; VBITS_EQ_256-LABEL: fminnm_v16f32:
; VBITS_EQ_256: // %bb.0:
-; VBITS_EQ_256-NEXT: mov x8, #8
+; VBITS_EQ_256-NEXT: mov x8, #8 // =0x8
; VBITS_EQ_256-NEXT: ptrue p0.s, vl8
; VBITS_EQ_256-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]
; VBITS_EQ_256-NEXT: ld1w { z1.s }, p0/z, [x0]
@@ -542,7 +542,7 @@ define void @fminnm_v4f64(ptr %a, ptr %b) vscale_range(2,0) #0 {
define void @fminnm_v8f64(ptr %a, ptr %b) #0 {
; VBITS_EQ_256-LABEL: fminnm_v8f64:
; VBITS_EQ_256: // %bb.0:
-; VBITS_EQ_256-NEXT: mov x8, #4
+; VBITS_EQ_256-NEXT: mov x8, #4 // =0x4
; VBITS_EQ_256-NEXT: ptrue p0.d, vl4
; VBITS_EQ_256-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]
; VBITS_EQ_256-NEXT: ld1d { z1.d }, p0/z, [x0]
@@ -644,7 +644,7 @@ define void @fmax_v16f16(ptr %a, ptr %b) vscale_range(2,0) #0 {
define void @fmax_v32f16(ptr %a, ptr %b) #0 {
; VBITS_EQ_256-LABEL: fmax_v32f16:
; VBITS_EQ_256: // %bb.0:
-; VBITS_EQ_256-NEXT: mov x8, #16
+; VBITS_EQ_256-NEXT: mov x8, #16 // =0x10
; VBITS_EQ_256-NEXT: ptrue p0.h, vl16
; VBITS_EQ_256-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]
; VBITS_EQ_256-NEXT: ld1h { z1.h }, p0/z, [x0]
@@ -742,7 +742,7 @@ define void @fmax_v8f32(ptr %a, ptr %b) vscale_range(2,0) #0 {
define void @fmax_v16f32(ptr %a, ptr %b) #0 {
; VBITS_EQ_256-LABEL: fmax_v16f32:
; VBITS_EQ_256: // %bb.0:
-; VBITS_EQ_256-NEXT: mov x8, #8
+; VBITS_EQ_256-NEXT: mov x8, #8 // =0x8
; VBITS_EQ_256-NEXT: ptrue p0.s, vl8
; VBITS_EQ_256-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]
; VBITS_EQ_256-NEXT: ld1w { z1.s }, p0/z, [x0]
@@ -840,7 +840,7 @@ define void @fmax_v4f64(ptr %a, ptr %b) vscale_range(2,0) #0 {
define void @fmax_v8f64(ptr %a, ptr %b) #0 {
; VBITS_EQ_256-LABEL: fmax_v8f64:
; VBITS_EQ_256: // %bb.0:
-; VBITS_EQ_256-NEXT: mov x8, #4
+; VBITS_EQ_256-NEXT: mov x8, #4 // =0x4
; VBITS_EQ_256-NEXT: ptrue p0.d, vl4
; VBITS_EQ_256-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]
; VBITS_EQ_256-NEXT: ld1d { z1.d }, p0/z, [x0]
@@ -942,7 +942,7 @@ define void @fmin_v16f16(ptr %a, ptr %b) vscale_range(2,0) #0 {
define void @fmin_v32f16(ptr %a, ptr %b) #0 {
; VBITS_EQ_256-LABEL: fmin_v32f16:
; VBITS_EQ_256: // %bb.0:
-; VBITS_EQ_256-NEXT: mov x8, #16
+; VBITS_EQ_256-NEXT: mov x8, #16 // =0x10
; VBITS_EQ_256-NEXT: ptrue p0.h, vl16
; VBITS_EQ_256-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]
; VBITS_EQ_256-NEXT: ld1h { z1.h }, p0/z, [x0]
@@ -1040,7 +1040,7 @@ define void @fmin_v8f32(ptr %a, ptr %b) vscale_range(2,0) #0 {
define void @fmin_v16f32(ptr %a, ptr %b) #0 {
; VBITS_EQ_256-LABEL: fmin_v16f32:
; VBITS_EQ_256: // %bb.0:
-; VBITS_EQ_256-NEXT: mov x8, #8
+; VBITS_EQ_256-NEXT: mov x8, #8 // =0x8
; VBITS_EQ_256-NEXT: ptrue p0.s, vl8
; VBITS_EQ_256-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]
; VBITS_EQ_256-NEXT: ld1w { z1.s }, p0/z, [x0]
@@ -1138,7 +1138,7 @@ define void @fmin_v4f64(ptr %a, ptr %b) vscale_range(2,0) #0 {
define void @fmin_v8f64(ptr %a, ptr %b) #0 {
; VBITS_EQ_256-LABEL: fmin_v8f64:
; VBITS_EQ_256: // %bb.0:
-; VBITS_EQ_256-NEXT: mov x8, #4
+; VBITS_EQ_256-NEXT: mov x8, #4 // =0x4
; VBITS_EQ_256-NEXT: ptrue p0.d, vl4
; VBITS_EQ_256-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]
; VBITS_EQ_256-NEXT: ld1d { z1.d }, p0/z, [x0]
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