[PATCH] D155472: [DAG] Attempt shl narrowing in SimplifyDemandedBits (WIP)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

@oakrc Nice! By caller-saved GPR contents do you mean intermediate register values? That should be expected as SimplifyDemandedBits can lead to undemanded bits from each register value changing.


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  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D155472/new/

https://reviews.llvm.org/D155472