[PATCH] D155472: [DAG] Attempt shl narrowing in SimplifyDemandedBits (WIP)

[Zhenkai Weng via Phabricator via llvm-commits]

oakrc added subscribers: Peter, oakrc.
oakrc added a comment.

@pengfei, @Peter told me about how these test cases can potentially be fuzzed to check for equivalence, and I've made a little script <https://github.com/SecurityLab-UCD/sempy> to compare generated X86 assemblies of simple function pairs (e.g. those without ptr parameters) by randomizing initial register values, emulating each function pair separately, and comparing final register values. Each function pair is emulated 1000 times using Unicorn Engine, although any difference in register value usually comes up in the first iteration. No function pair I've tested so far has presented a discrepancy in return value (`%rax`), though some do present a difference in caller-saved GPR contents (`%rdi`, `%rcx`, `%rsi`, `%r8`). The list of functions that I were able to verify is as follows:

`llvm/test/CodeGen/X86/bswap.ll`

- `not_bswap`
- `not_useful_bswap`
- `finally_useful_bswap`

`llvm/test/CodeGen/X86/cmp-concat.ll`

- `cmp_anybits_concat_shl_shl_i16`
- `cmp_anybits_concat_shl_shl_i16_commute`

`llvm/test/CodeGen/X86/combine-bitreverse.ll`

- `test_bitreverse_shli_bitreverse_i64`

`llvm/test/CodeGen/X86/const-shift-of-constmasked.ll`

- `test_i64_2147483647_mask_shl_1`

`llvm/test/CodeGen/X86/dagcombine-shifts.ll`

- `fun7`
- `fun8`
- `fun11`
- `fun12`

`llvm/test/CodeGen/X86/divmod128.ll`

- `urem_i128_12` (x86-64)
- `urem_i128_12` (win64)

`llvm/test/CodeGen/X86/extract-bits.ll`

- `c2_i64`

`llvm/test/CodeGen/X86/lea-dagdag.ll`

- `and_i32_zext_shl_add_i64_overshift`

`llvm/test/CodeGen/X86/lea-opt2.ll`

- `test9`

`llvm/test/CodeGen/X86/parity.ll`

- `parity_64_shift` (nopopcnt)

`llvm/test/CodeGen/X86/select.ll`

- `select_pow2_diff_neg_invert`

`llvm/test/CodeGen/X86/selectcc-to-shiftand.ll`

- `sel_shift_bool_i64`

`llvm/test/CodeGen/X86/setcc.ll`

- `t3`

`llvm/test/CodeGen/X86/shift-combine.ll`

- `test_lshr_and`

`llvm/test/CodeGen/X86/shift-pair.ll`

- `test`

`llvm/test/CodeGen/X86/zext-shl.ll`

- `i64_zext_shift_i16_zext_i8`
- `i128_zext_shift_i64_zext_i8`
- `i128_zext_shift_i64_zext_i16`




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https://reviews.llvm.org/D155472