[PATCH] D76051: [RISCV][GlobalISel] Select register banks for GPR ALU instructions

[Craig Topper via Phabricator via llvm-commits]

craig.topper updated this revision to Diff 551703.
craig.topper added a comment.

Change back to using Subtarget to get register size. I think even with s32 being legal
on RV64 we still want to use a 64 bit size for the GPR.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D76051/new/

https://reviews.llvm.org/D76051

Files:
  llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
  llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.h
  llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv32.mir
  llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv64.mir
  llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv32.mir
  llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv64.mir

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