[PATCH] D158138: [RISCV] Expand PseudoTAIL with t2 instead of t1 for Zicfilp.
Jessica Clarke via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 16 19:31:30 PDT 2023
jrtc27 added a comment.
Oh I see, https://github.com/riscv/riscv-cfi/blob/main/cfi_forward.adoc does. Why on earth did they pick x7 for tail when x6 is the register defined for tail?
Repository:
rG LLVM Github Monorepo
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https://reviews.llvm.org/D158138/new/
https://reviews.llvm.org/D158138
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