[PATCH] D158138: [RISCV] Expand PseudoTAIL with t2 instead of t1 for Zicfilp.

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added a comment.

https://github.com/riscv-non-isa/riscv-asm-manual/blob/master/riscv-asm.md#-a-listing-of-standard-risc-v-pseudoinstructions very clearly states that x6 is the register used. What's wrong with t1? x1 and x5 are special as the registers for microarchitectural push/pop hints and, with Zicfilp, repurposed for shadow stack push/pop (somewhat ew), but neither x6 nor x7 are mentioned in the CFI spec that I can see.


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  https://reviews.llvm.org/D158138/new/

https://reviews.llvm.org/D158138