[PATCH] D158062: [RISCV] Teach RISCVMergeBaseOffset to handle inline asm

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp:398
+    }
+    case RISCV::INLINEASM: {
+      unsigned NumOps = 0;
----------------
What about INLINEASM_BR?


================
Comment at: llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp:427
+        CommonOffset = Offset;
+        InlineAsmMemoryOpIndexes.push_back(I + 1);
+      }
----------------
If there are multiple INLINE_ASM instructions, would InlineAsmMemoryOpIndexes need to know which instruction the index belong to?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158062/new/

https://reviews.llvm.org/D158062