[llvm] c5f763b - [AArch64][GISel] Fix selection of G_CONSTANT_FOLD_BARRIER

[David Green via llvm-commits]

Author: David Green
Date: 2023-08-16T08:33:16+01:00
New Revision: c5f763b563e37ebe26bfd4a012269482d54d0a80

URL: https://github.com/llvm/llvm-project/commit/c5f763b563e37ebe26bfd4a012269482d54d0a80
DIFF: https://github.com/llvm/llvm-project/commit/c5f763b563e37ebe26bfd4a012269482d54d0a80.diff

LOG: [AArch64][GISel] Fix selection of G_CONSTANT_FOLD_BARRIER

As far as I understand - When lowering a G_CONSTANT_FOLD_BARRIER we replace the
DstReg with SrcReg, and need to check that the register class is equivalent
when doing so for the replacement to be legal. During lowering we could end up
visiting nodes in an odd order, leaving a G_CONSTANT_FOLD_BARRIER with a known
regclass for the src, but only a regbank for the dst. Providing the Regbank
contains the regclass, the replacement should still be safe.

This fixes an assert seen in the llvm-test-suite when lowering hoisted
constants, relaxing canReplaceReg to account for the case when the regbank
covers the regclass, so it is better able to handle differences in visiting
order.

Differential Revision: https://reviews.llvm.org/D157202

Added: 
    llvm/test/CodeGen/AArch64/GlobalISel/select-constbarrier.mir

Modified: 
    llvm/lib/CodeGen/GlobalISel/Utils.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/GlobalISel/Utils.cpp b/llvm/lib/CodeGen/GlobalISel/Utils.cpp
index 080600d3cc986c..862cc60fb1e95a 100644
--- a/llvm/lib/CodeGen/GlobalISel/Utils.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/Utils.cpp
@@ -205,8 +205,15 @@ bool llvm::canReplaceReg(Register DstReg, Register SrcReg,
     return false;
   // Replace if either DstReg has no constraints or the register
   // constraints match.
-  return !MRI.getRegClassOrRegBank(DstReg) ||
-         MRI.getRegClassOrRegBank(DstReg) == MRI.getRegClassOrRegBank(SrcReg);
+  const auto &DstRBC = MRI.getRegClassOrRegBank(DstReg);
+  if (!DstRBC || DstRBC == MRI.getRegClassOrRegBank(SrcReg))
+    return true;
+
+  // Otherwise match if the Src is already a regclass that is covered by the Dst
+  // RegBank.
+  return DstRBC.is<const RegisterBank *>() && MRI.getRegClassOrNull(SrcReg) &&
+         DstRBC.get<const RegisterBank *>()->covers(
+             *MRI.getRegClassOrNull(SrcReg));
 }
 
 bool llvm::isTriviallyDead(const MachineInstr &MI,

diff  --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-constbarrier.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-constbarrier.mir
new file mode 100644
index 00000000000000..f5290a5edc0128
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-constbarrier.mir
@@ -0,0 +1,58 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name:            test
+legalized:       true
+regBankSelected: true
+selected:        false
+tracksRegLiveness: true
+body:             |
+  ; CHECK-LABEL: name: test
+  ; CHECK: bb.0:
+  ; CHECK-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
+  ; CHECK-NEXT:   liveins: $w0, $w1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 145185
+  ; CHECK-NEXT:   TBNZW [[MOVi32imm]], 0, %bb.2
+  ; CHECK-NEXT:   B %bb.1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1:
+  ; CHECK-NEXT:   successors: %bb.3(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   $w5 = COPY [[MOVi32imm]]
+  ; CHECK-NEXT:   B %bb.3
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2:
+  ; CHECK-NEXT:   successors: %bb.3(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[MOVi32imm]], [[MOVi32imm]]
+  ; CHECK-NEXT:   $w3 = COPY [[ADDWrr]]
+  ; CHECK-NEXT:   B %bb.3
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.3:
+  ; CHECK-NEXT:   RET_ReallyLR
+  bb.0:
+    successors: %bb.4(0x40000000), %bb.3(0x40000000)
+    liveins: $w0, $w1
+
+    %35:gpr(s32) = G_CONSTANT i32 145185
+    G_BRCOND %35(s32), %bb.4
+    G_BR %bb.3
+
+  bb.3:
+    successors: %bb.5(0x80000000)
+
+    %17:gpr(s32) = G_CONSTANT_FOLD_BARRIER %35
+    $w5 = COPY %17(s32)
+    G_BR %bb.5
+
+  bb.4:
+    successors: %bb.5(0x80000000)
+
+    %23:gpr(s32) = G_ADD %35, %35
+    $w3 = COPY %23(s32)
+    G_BR %bb.5
+
+  bb.5:
+    RET_ReallyLR