[PATCH] D157886: [RISCV] Match strided loads with reversed indexing sequences

Luke Lau via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Aug 15 03:08:05 PDT 2023


luke added a comment.

Makes sense to me



================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:12818
   Align Align = BaseLd->getAlign();
-
   for (SDValue Op : N->ops().drop_front()) {
     auto *Ld = dyn_cast<LoadSDNode>(Op);
----------------
Can we do `for (SDValue Op : N->ops())` instead to remove the need for the extra isSimple() and isNormalLoad() checks above?


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:12833
+    SDValue Stride;
+    for (auto Idx : enumerate(Ptrs)) {
+      if (Idx.index() == 0)
----------------
Just an idea, can we use one lambda and pass in a reverse iterator of the Ptrs vector?


================
Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-combine.ll:497
 
 ; TODO: This is a strided load with a negative stride
 define void @reverse_strided_constant_pos_4xv2f32(ptr %x, ptr %z, i64 %s) {
----------------
We can strike off this todo


Repository:
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https://reviews.llvm.org/D157886



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