[PATCH] D157886: [RISCV] Match strided loads with reversed indexing sequences

[Philip Reames via Phabricator via llvm-commits]

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This extends the concat_vector of loads to strided_load transform to handle reversed index pattern.  The previous code expected indexing of the form (a0, a1+S, a2+S,...).  However, we can also see indexing of the form (a1+S, a2+S, a3+S, .., aS).  This form is a strided load starting at address aN + S*(n-1) with stride -S.

Note that this is also fixing what looks to be a bug in the memory location reasoning for forward strided case.  A strided load with negative stride access eltsize bytes past base ptr, and then bytes *before* base ptr.  (That is, the range should extend from before base ptr to after base ptr.)


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D157886

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-combine.ll

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