[PATCH] D156538: [AArch64] Try to combine FMUL with FDIV

[JinGu Kang via Phabricator via llvm-commits]

jaykang10 added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64InstrFormats.td:5041
 
   def SXSri: BaseIntegerToFP<isUnsigned, GPR64, FPR32, fixedpoint_f32_i64, asm,
                              [(set FPR32:$Rd,
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dmgreen wrote:
> Should these be recip too? I'm not sure they need to be, but it might be better for them to be consistent.
Sorry for mistake. I did not update it.
It looks the TableGen does not complain about the inconsistency between complex pattern operands in `InOperandList` and `Pattern`.
As you mentioned, it would be just good to use same thing for consistent.


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  https://reviews.llvm.org/D156538/new/

https://reviews.llvm.org/D156538