[PATCH] D157943: [GlobalISel][Mips] Correct corner case in G_UADDE legalization.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: arsenm, aemerson, atanasyan, dsanders, Petar.Avramovic.
Herald added subscribers: jrtc27, hiraditya, arichardson, sdardis.
Herald added a project: All.
craig.topper requested review of this revision.
Herald added a subscriber: wdng.
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If carryin was 1, and RHS is 0xffffffff we were not giving a carry
out.

In that case Res would be equal to LHS, so Res <u LHS would be false.
But there should be a carry out since carryin+RHS wraps around to 0.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D157943

Files:
  llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
  llvm/test/CodeGen/Mips/GlobalISel/legalizer/add.mir
  llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll


Index: llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll
===================================================================
--- llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll
+++ llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll
@@ -115,13 +115,21 @@
 ; MIPS32-NEXT:    addu $2, $2, $8
 ; MIPS32-NEXT:    sltu $8, $2, $8
 ; MIPS32-NEXT:    addu $3, $6, $3
-; MIPS32-NEXT:    andi $8, $8, 1
-; MIPS32-NEXT:    addu $3, $3, $8
+; MIPS32-NEXT:    andi $9, $8, 1
+; MIPS32-NEXT:    addu $3, $3, $9
+; MIPS32-NEXT:    xor $9, $3, $6
+; MIPS32-NEXT:    sltiu $9, $9, 1
 ; MIPS32-NEXT:    sltu $6, $3, $6
+; MIPS32-NEXT:    andi $9, $9, 1
+; MIPS32-NEXT:    movn $6, $8, $9
 ; MIPS32-NEXT:    addu $4, $5, $4
-; MIPS32-NEXT:    andi $6, $6, 1
-; MIPS32-NEXT:    addu $4, $4, $6
+; MIPS32-NEXT:    andi $8, $6, 1
+; MIPS32-NEXT:    addu $4, $4, $8
+; MIPS32-NEXT:    xor $8, $4, $5
+; MIPS32-NEXT:    sltiu $8, $8, 1
 ; MIPS32-NEXT:    sltu $5, $4, $5
+; MIPS32-NEXT:    andi $8, $8, 1
+; MIPS32-NEXT:    movn $5, $6, $8
 ; MIPS32-NEXT:    addu $1, $1, $7
 ; MIPS32-NEXT:    andi $5, $5, 1
 ; MIPS32-NEXT:    addu $5, $1, $5
Index: llvm/test/CodeGen/Mips/GlobalISel/legalizer/add.mir
===================================================================
--- llvm/test/CodeGen/Mips/GlobalISel/legalizer/add.mir
+++ llvm/test/CodeGen/Mips/GlobalISel/legalizer/add.mir
@@ -265,14 +265,20 @@
     ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
     ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]]
     ; MIPS32: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[AND]]
-    ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD2]](s32), [[LOAD1]]
-    ; MIPS32: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[LOAD2]], [[COPY2]]
+    ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ADD2]](s32), [[LOAD1]]
+    ; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD2]](s32), [[LOAD1]]
     ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C]]
-    ; MIPS32: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[AND1]]
-    ; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD4]](s32), [[LOAD2]]
+    ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s32), [[ICMP]], [[ICMP2]]
+    ; MIPS32: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[LOAD2]], [[COPY2]]
+    ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C]]
+    ; MIPS32: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[AND2]]
+    ; MIPS32: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ADD4]](s32), [[LOAD2]]
+    ; MIPS32: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD4]](s32), [[LOAD2]]
+    ; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ICMP3]], [[C]]
+    ; MIPS32: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[AND3]](s32), [[SELECT]], [[ICMP4]]
     ; MIPS32: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[LOAD3]], [[COPY3]]
-    ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ICMP2]], [[C]]
-    ; MIPS32: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[ADD5]], [[AND2]]
+    ; MIPS32: [[AND4:%[0-9]+]]:_(s32) = G_AND [[SELECT1]], [[C]]
+    ; MIPS32: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[ADD5]], [[AND4]]
     ; MIPS32: $v0 = COPY [[ADD]](s32)
     ; MIPS32: $v1 = COPY [[ADD2]](s32)
     ; MIPS32: $a0 = COPY [[ADD4]](s32)
Index: llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
===================================================================
--- llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -3436,12 +3436,16 @@
   }
   case G_UADDE: {
     auto [Res, CarryOut, LHS, RHS, CarryIn] = MI.getFirst5Regs();
-    LLT Ty = MRI.getType(Res);
+    const LLT CondTy = MRI.getType(CarryOut);
+    const LLT Ty = MRI.getType(Res);
 
     auto TmpRes = MIRBuilder.buildAdd(Ty, LHS, RHS);
     auto ZExtCarryIn = MIRBuilder.buildZExt(Ty, CarryIn);
     MIRBuilder.buildAdd(Res, TmpRes, ZExtCarryIn);
-    MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, LHS);
+
+    auto Res_EQ_LHS = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, CondTy, Res, LHS);
+    auto Res_ULT_LHS = MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CondTy, Res, LHS);
+    MIRBuilder.buildSelect(CarryOut, Res_EQ_LHS, CarryIn, Res_ULT_LHS);
 
     MI.eraseFromParent();
     return Legalized;


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