[PATCH] D157847: [RISCV] Fix assertion when passing f64 vectors via integer registers

[Alex Bradbury via Phabricator via llvm-commits]

asb added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/pr64645.ll:5
+
+define <2 x double> @v2f64(<2 x double> %x, <2 x double> %y) {
+; CHECK-LABEL: v2f64:
----------------
Nit: we'd normally at `nounwind` here as there's nothing we're specifically trying to test about the .cfi stuff.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D157847/new/

https://reviews.llvm.org/D157847