[PATCH] D157847: [RISCV] Fix assertion when passing f64 vectors via integer registers

[Wang Pengcheng via Phabricator via llvm-commits]

wangpc marked an inline comment as done.
wangpc added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/pr64645.ll:8
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    ret
+  ret <2 x double> %x
----------------
liaolucy wrote:
> I have a question, do I need to load and store from the stack here?
> ```
> eg:
>         lw      a2, 12(a1)
>         lw      a3, 8(a1)
>         lw      a4, 4(a1)
>         lw      a1, 0(a1)
>         sw      a2, 12(a0)
>         sw      a3, 8(a0)
>         sw      a4, 4(a0)
>         sw      a1, 0(a0)
> ```
The previous test can generate load/store after ISel but these load/store will be deleted during RA as they are not used.
As @asb suggested, I added some operations on arguments so the lowering of arguments will be visible.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D157847/new/

https://reviews.llvm.org/D157847