[llvm] d199478 - [AArch64][GISel] Handling for G_VECREDUCE_FMIN and G_VECREDUCE_FMAX
David Green via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 14 01:19:53 PDT 2023
Author: David Green
Date: 2023-08-14T09:19:47+01:00
New Revision: d199478af48ada4b7be7c4862b8782cb3093ad93
URL: https://github.com/llvm/llvm-project/commit/d199478af48ada4b7be7c4862b8782cb3093ad93
DIFF: https://github.com/llvm/llvm-project/commit/d199478af48ada4b7be7c4862b8782cb3093ad93.diff
LOG: [AArch64][GISel] Handling for G_VECREDUCE_FMIN and G_VECREDUCE_FMAX
This adds legalization for G_VECREDUCE_FMIN and G_VECREDUCE_FMAX, where the
selection can go via tablegen patterns. I haven't tried to get non-power2 types
working yet, just the more legal types.
Differential Revision: https://reviews.llvm.org/D156614
Added:
Modified:
llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization-nan.ll
llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization.ll
llvm/test/CodeGen/AArch64/vecreduce-fmin-legalization.ll
Removed:
################################################################################
diff --git a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
index 2fad0893f45fab..9e3a3e25d8ee57 100644
--- a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
+++ b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
@@ -163,6 +163,8 @@ def : GINodeEquiv<G_ROTL, rotl>;
def : GINodeEquiv<G_LROUND, lround>;
def : GINodeEquiv<G_LLROUND, llround>;
def : GINodeEquiv<G_VECREDUCE_FADD, vecreduce_fadd>;
+def : GINodeEquiv<G_VECREDUCE_FMAX, vecreduce_fmax>;
+def : GINodeEquiv<G_VECREDUCE_FMIN, vecreduce_fmin>;
def : GINodeEquiv<G_STRICT_FADD, strict_fadd>;
def : GINodeEquiv<G_STRICT_FSUB, strict_fsub>;
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index 5a93bb9c32eaaf..59daea97abd9eb 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -2647,6 +2647,20 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
Observer.changedInstr(MI);
return Legalized;
}
+ case TargetOpcode::G_VECREDUCE_FMIN:
+ case TargetOpcode::G_VECREDUCE_FMAX:
+ if (TypeIdx != 0)
+ return UnableToLegalize;
+ Observer.changingInstr(MI);
+ Register VecReg = MI.getOperand(1).getReg();
+ LLT VecTy = MRI.getType(VecReg);
+ LLT WideVecTy = VecTy.isVector()
+ ? LLT::vector(VecTy.getElementCount(), WideTy)
+ : WideTy;
+ widenScalarSrc(MI, WideVecTy, 1, TargetOpcode::G_FPEXT);
+ widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC);
+ Observer.changedInstr(MI);
+ return Legalized;
}
}
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 3b4f893e650f7f..e9865e951a15a8 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -850,6 +850,18 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.clampMaxNumElements(1, s32, 4)
.lower();
+ getActionDefinitionsBuilder({G_VECREDUCE_FMIN, G_VECREDUCE_FMAX})
+ .legalFor({{s32, v4s32}, {s32, v2s32}, {s64, v2s64}})
+ .legalIf([=](const LegalityQuery &Query) {
+ const auto &Ty = Query.Types[1];
+ return Query.Types[0] == s16 && (Ty == v8s16 || Ty == v4s16) && HasFP16;
+ })
+ .minScalarOrElt(0, MinFPScalar)
+ .clampMaxNumElements(1, s64, 2)
+ .clampMaxNumElements(1, s32, 4)
+ .clampMaxNumElements(1, s16, 8)
+ .lower();
+
getActionDefinitionsBuilder(
{G_VECREDUCE_OR, G_VECREDUCE_AND, G_VECREDUCE_XOR})
// Try to break down into smaller vectors as long as they're at least 64
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
index 89c22d79c9332a..410bfc12f83e4f 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
@@ -720,11 +720,12 @@
# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
# DEBUG-NEXT: G_VECREDUCE_FMAX (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
-# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
-# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
+# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
+# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: G_VECREDUCE_FMIN (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
-# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
-# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
+# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: G_VECREDUCE_ADD (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
diff --git a/llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization-nan.ll b/llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization-nan.ll
index 138671670b652e..2b1927ff644691 100644
--- a/llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization-nan.ll
+++ b/llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization-nan.ll
@@ -1,6 +1,20 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NOFP
-; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon,+fullfp16 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FP
+; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NOFP --check-prefix=CHECK-NOFP-SD
+; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon,+fullfp16 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FP --check-prefix=CHECK-FP-SD
+; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NOFP --check-prefix=CHECK-NOFP-GI
+; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon,+fullfp16 -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FP --check-prefix=CHECK-FP-GI
+
+; CHECK-NOFP-GI: warning: Instruction selection used fallback path for test_v11f16
+; CHECK-NOFP-GI-NEXT: warning: Instruction selection used fallback path for test_v11f16_ninf
+; CHECK-NOFP-GI-NEXT: warning: Instruction selection used fallback path for test_v3f32
+; CHECK-NOFP-GI-NEXT: warning: Instruction selection used fallback path for test_v3f32_ninf
+; CHECK-NOFP-GI-NEXT: warning: Instruction selection used fallback path for test_v2f128
+;
+; CHECK-FP-GI: warning: Instruction selection used fallback path for test_v11f16
+; CHECK-FP-GI-NEXT: warning: Instruction selection used fallback path for test_v11f16_ninf
+; CHECK-FP-GI-NEXT: warning: Instruction selection used fallback path for test_v3f32
+; CHECK-FP-GI-NEXT: warning: Instruction selection used fallback path for test_v3f32_ninf
+; CHECK-FP-GI-NEXT: warning: Instruction selection used fallback path for test_v2f128
declare half @llvm.vector.reduce.fmax.v1f16(<1 x half> %a)
declare float @llvm.vector.reduce.fmax.v1f32(<1 x float> %a)
@@ -30,11 +44,29 @@ define half @test_v1f16(<1 x half> %a) nounwind {
}
define float @test_v1f32(<1 x float> %a) nounwind {
-; CHECK-LABEL: test_v1f32:
-; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
-; CHECK-NEXT: ret
+; CHECK-NOFP-SD-LABEL: test_v1f32:
+; CHECK-NOFP-SD: // %bb.0:
+; CHECK-NOFP-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NOFP-SD-NEXT: // kill: def $s0 killed $s0 killed $q0
+; CHECK-NOFP-SD-NEXT: ret
+;
+; CHECK-FP-SD-LABEL: test_v1f32:
+; CHECK-FP-SD: // %bb.0:
+; CHECK-FP-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP-SD-NEXT: // kill: def $s0 killed $s0 killed $q0
+; CHECK-FP-SD-NEXT: ret
+;
+; CHECK-NOFP-GI-LABEL: test_v1f32:
+; CHECK-NOFP-GI: // %bb.0:
+; CHECK-NOFP-GI-NEXT: fmov x8, d0
+; CHECK-NOFP-GI-NEXT: fmov s0, w8
+; CHECK-NOFP-GI-NEXT: ret
+;
+; CHECK-FP-GI-LABEL: test_v1f32:
+; CHECK-FP-GI: // %bb.0:
+; CHECK-FP-GI-NEXT: fmov x8, d0
+; CHECK-FP-GI-NEXT: fmov s0, w8
+; CHECK-FP-GI-NEXT: ret
%b = call float @llvm.vector.reduce.fmax.v1f32(<1 x float> %a)
ret float %b
}
@@ -56,195 +88,231 @@ define fp128 @test_v1f128(<1 x fp128> %a) nounwind {
}
define half @test_v4f16(<4 x half> %a) nounwind {
-; CHECK-NOFP-LABEL: test_v4f16:
-; CHECK-NOFP: // %bb.0:
-; CHECK-NOFP-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NOFP-NEXT: mov h1, v0.h[1]
-; CHECK-NOFP-NEXT: fcvt s2, h0
-; CHECK-NOFP-NEXT: fcvt s1, h1
-; CHECK-NOFP-NEXT: fmaxnm s1, s2, s1
-; CHECK-NOFP-NEXT: mov h2, v0.h[2]
-; CHECK-NOFP-NEXT: mov h0, v0.h[3]
-; CHECK-NOFP-NEXT: fcvt h1, s1
-; CHECK-NOFP-NEXT: fcvt s2, h2
-; CHECK-NOFP-NEXT: fcvt s0, h0
-; CHECK-NOFP-NEXT: fcvt s1, h1
-; CHECK-NOFP-NEXT: fmaxnm s1, s1, s2
-; CHECK-NOFP-NEXT: fcvt h1, s1
-; CHECK-NOFP-NEXT: fcvt s1, h1
-; CHECK-NOFP-NEXT: fmaxnm s0, s1, s0
-; CHECK-NOFP-NEXT: fcvt h0, s0
-; CHECK-NOFP-NEXT: ret
+; CHECK-NOFP-SD-LABEL: test_v4f16:
+; CHECK-NOFP-SD: // %bb.0:
+; CHECK-NOFP-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NOFP-SD-NEXT: mov h1, v0.h[1]
+; CHECK-NOFP-SD-NEXT: fcvt s2, h0
+; CHECK-NOFP-SD-NEXT: fcvt s1, h1
+; CHECK-NOFP-SD-NEXT: fmaxnm s1, s2, s1
+; CHECK-NOFP-SD-NEXT: mov h2, v0.h[2]
+; CHECK-NOFP-SD-NEXT: mov h0, v0.h[3]
+; CHECK-NOFP-SD-NEXT: fcvt h1, s1
+; CHECK-NOFP-SD-NEXT: fcvt s2, h2
+; CHECK-NOFP-SD-NEXT: fcvt s0, h0
+; CHECK-NOFP-SD-NEXT: fcvt s1, h1
+; CHECK-NOFP-SD-NEXT: fmaxnm s1, s1, s2
+; CHECK-NOFP-SD-NEXT: fcvt h1, s1
+; CHECK-NOFP-SD-NEXT: fcvt s1, h1
+; CHECK-NOFP-SD-NEXT: fmaxnm s0, s1, s0
+; CHECK-NOFP-SD-NEXT: fcvt h0, s0
+; CHECK-NOFP-SD-NEXT: ret
;
; CHECK-FP-LABEL: test_v4f16:
; CHECK-FP: // %bb.0:
; CHECK-FP-NEXT: fmaxnmv h0, v0.4h
; CHECK-FP-NEXT: ret
+;
+; CHECK-NOFP-GI-LABEL: test_v4f16:
+; CHECK-NOFP-GI: // %bb.0:
+; CHECK-NOFP-GI-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-NOFP-GI-NEXT: fmaxnmv s0, v0.4s
+; CHECK-NOFP-GI-NEXT: fcvt h0, s0
+; CHECK-NOFP-GI-NEXT: ret
%b = call half @llvm.vector.reduce.fmax.v4f16(<4 x half> %a)
ret half %b
}
define half @test_v4f16_ninf(<4 x half> %a) nounwind {
-; CHECK-NOFP-LABEL: test_v4f16_ninf:
-; CHECK-NOFP: // %bb.0:
-; CHECK-NOFP-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NOFP-NEXT: mov h1, v0.h[1]
-; CHECK-NOFP-NEXT: fcvt s2, h0
-; CHECK-NOFP-NEXT: fcvt s1, h1
-; CHECK-NOFP-NEXT: fmaxnm s1, s2, s1
-; CHECK-NOFP-NEXT: mov h2, v0.h[2]
-; CHECK-NOFP-NEXT: mov h0, v0.h[3]
-; CHECK-NOFP-NEXT: fcvt h1, s1
-; CHECK-NOFP-NEXT: fcvt s2, h2
-; CHECK-NOFP-NEXT: fcvt s0, h0
-; CHECK-NOFP-NEXT: fcvt s1, h1
-; CHECK-NOFP-NEXT: fmaxnm s1, s1, s2
-; CHECK-NOFP-NEXT: fcvt h1, s1
-; CHECK-NOFP-NEXT: fcvt s1, h1
-; CHECK-NOFP-NEXT: fmaxnm s0, s1, s0
-; CHECK-NOFP-NEXT: fcvt h0, s0
-; CHECK-NOFP-NEXT: ret
+; CHECK-NOFP-SD-LABEL: test_v4f16_ninf:
+; CHECK-NOFP-SD: // %bb.0:
+; CHECK-NOFP-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NOFP-SD-NEXT: mov h1, v0.h[1]
+; CHECK-NOFP-SD-NEXT: fcvt s2, h0
+; CHECK-NOFP-SD-NEXT: fcvt s1, h1
+; CHECK-NOFP-SD-NEXT: fmaxnm s1, s2, s1
+; CHECK-NOFP-SD-NEXT: mov h2, v0.h[2]
+; CHECK-NOFP-SD-NEXT: mov h0, v0.h[3]
+; CHECK-NOFP-SD-NEXT: fcvt h1, s1
+; CHECK-NOFP-SD-NEXT: fcvt s2, h2
+; CHECK-NOFP-SD-NEXT: fcvt s0, h0
+; CHECK-NOFP-SD-NEXT: fcvt s1, h1
+; CHECK-NOFP-SD-NEXT: fmaxnm s1, s1, s2
+; CHECK-NOFP-SD-NEXT: fcvt h1, s1
+; CHECK-NOFP-SD-NEXT: fcvt s1, h1
+; CHECK-NOFP-SD-NEXT: fmaxnm s0, s1, s0
+; CHECK-NOFP-SD-NEXT: fcvt h0, s0
+; CHECK-NOFP-SD-NEXT: ret
;
; CHECK-FP-LABEL: test_v4f16_ninf:
; CHECK-FP: // %bb.0:
; CHECK-FP-NEXT: fmaxnmv h0, v0.4h
; CHECK-FP-NEXT: ret
+;
+; CHECK-NOFP-GI-LABEL: test_v4f16_ninf:
+; CHECK-NOFP-GI: // %bb.0:
+; CHECK-NOFP-GI-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-NOFP-GI-NEXT: fmaxnmv s0, v0.4s
+; CHECK-NOFP-GI-NEXT: fcvt h0, s0
+; CHECK-NOFP-GI-NEXT: ret
%b = call ninf half @llvm.vector.reduce.fmax.v4f16(<4 x half> %a)
ret half %b
}
define half @test_v8f16(<8 x half> %a) nounwind {
-; CHECK-NOFP-LABEL: test_v8f16:
-; CHECK-NOFP: // %bb.0:
-; CHECK-NOFP-NEXT: mov h1, v0.h[1]
-; CHECK-NOFP-NEXT: fcvt s2, h0
-; CHECK-NOFP-NEXT: fcvt s1, h1
-; CHECK-NOFP-NEXT: fmaxnm s1, s2, s1
-; CHECK-NOFP-NEXT: mov h2, v0.h[2]
-; CHECK-NOFP-NEXT: fcvt h1, s1
-; CHECK-NOFP-NEXT: fcvt s2, h2
-; CHECK-NOFP-NEXT: fcvt s1, h1
-; CHECK-NOFP-NEXT: fmaxnm s1, s1, s2
-; CHECK-NOFP-NEXT: mov h2, v0.h[3]
-; CHECK-NOFP-NEXT: fcvt h1, s1
-; CHECK-NOFP-NEXT: fcvt s2, h2
-; CHECK-NOFP-NEXT: fcvt s1, h1
-; CHECK-NOFP-NEXT: fmaxnm s1, s1, s2
-; CHECK-NOFP-NEXT: mov h2, v0.h[4]
-; CHECK-NOFP-NEXT: fcvt h1, s1
-; CHECK-NOFP-NEXT: fcvt s2, h2
-; CHECK-NOFP-NEXT: fcvt s1, h1
-; CHECK-NOFP-NEXT: fmaxnm s1, s1, s2
-; CHECK-NOFP-NEXT: mov h2, v0.h[5]
-; CHECK-NOFP-NEXT: fcvt h1, s1
-; CHECK-NOFP-NEXT: fcvt s2, h2
-; CHECK-NOFP-NEXT: fcvt s1, h1
-; CHECK-NOFP-NEXT: fmaxnm s1, s1, s2
-; CHECK-NOFP-NEXT: mov h2, v0.h[6]
-; CHECK-NOFP-NEXT: mov h0, v0.h[7]
-; CHECK-NOFP-NEXT: fcvt h1, s1
-; CHECK-NOFP-NEXT: fcvt s2, h2
-; CHECK-NOFP-NEXT: fcvt s0, h0
-; CHECK-NOFP-NEXT: fcvt s1, h1
-; CHECK-NOFP-NEXT: fmaxnm s1, s1, s2
-; CHECK-NOFP-NEXT: fcvt h1, s1
-; CHECK-NOFP-NEXT: fcvt s1, h1
-; CHECK-NOFP-NEXT: fmaxnm s0, s1, s0
-; CHECK-NOFP-NEXT: fcvt h0, s0
-; CHECK-NOFP-NEXT: ret
+; CHECK-NOFP-SD-LABEL: test_v8f16:
+; CHECK-NOFP-SD: // %bb.0:
+; CHECK-NOFP-SD-NEXT: mov h1, v0.h[1]
+; CHECK-NOFP-SD-NEXT: fcvt s2, h0
+; CHECK-NOFP-SD-NEXT: fcvt s1, h1
+; CHECK-NOFP-SD-NEXT: fmaxnm s1, s2, s1
+; CHECK-NOFP-SD-NEXT: mov h2, v0.h[2]
+; CHECK-NOFP-SD-NEXT: fcvt h1, s1
+; CHECK-NOFP-SD-NEXT: fcvt s2, h2
+; CHECK-NOFP-SD-NEXT: fcvt s1, h1
+; CHECK-NOFP-SD-NEXT: fmaxnm s1, s1, s2
+; CHECK-NOFP-SD-NEXT: mov h2, v0.h[3]
+; CHECK-NOFP-SD-NEXT: fcvt h1, s1
+; CHECK-NOFP-SD-NEXT: fcvt s2, h2
+; CHECK-NOFP-SD-NEXT: fcvt s1, h1
+; CHECK-NOFP-SD-NEXT: fmaxnm s1, s1, s2
+; CHECK-NOFP-SD-NEXT: mov h2, v0.h[4]
+; CHECK-NOFP-SD-NEXT: fcvt h1, s1
+; CHECK-NOFP-SD-NEXT: fcvt s2, h2
+; CHECK-NOFP-SD-NEXT: fcvt s1, h1
+; CHECK-NOFP-SD-NEXT: fmaxnm s1, s1, s2
+; CHECK-NOFP-SD-NEXT: mov h2, v0.h[5]
+; CHECK-NOFP-SD-NEXT: fcvt h1, s1
+; CHECK-NOFP-SD-NEXT: fcvt s2, h2
+; CHECK-NOFP-SD-NEXT: fcvt s1, h1
+; CHECK-NOFP-SD-NEXT: fmaxnm s1, s1, s2
+; CHECK-NOFP-SD-NEXT: mov h2, v0.h[6]
+; CHECK-NOFP-SD-NEXT: mov h0, v0.h[7]
+; CHECK-NOFP-SD-NEXT: fcvt h1, s1
+; CHECK-NOFP-SD-NEXT: fcvt s2, h2
+; CHECK-NOFP-SD-NEXT: fcvt s0, h0
+; CHECK-NOFP-SD-NEXT: fcvt s1, h1
+; CHECK-NOFP-SD-NEXT: fmaxnm s1, s1, s2
+; CHECK-NOFP-SD-NEXT: fcvt h1, s1
+; CHECK-NOFP-SD-NEXT: fcvt s1, h1
+; CHECK-NOFP-SD-NEXT: fmaxnm s0, s1, s0
+; CHECK-NOFP-SD-NEXT: fcvt h0, s0
+; CHECK-NOFP-SD-NEXT: ret
;
; CHECK-FP-LABEL: test_v8f16:
; CHECK-FP: // %bb.0:
; CHECK-FP-NEXT: fmaxnmv h0, v0.8h
; CHECK-FP-NEXT: ret
+;
+; CHECK-NOFP-GI-LABEL: test_v8f16:
+; CHECK-NOFP-GI: // %bb.0:
+; CHECK-NOFP-GI-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-NOFP-GI-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-NOFP-GI-NEXT: fmaxnm v0.4s, v1.4s, v0.4s
+; CHECK-NOFP-GI-NEXT: fmaxnmv s0, v0.4s
+; CHECK-NOFP-GI-NEXT: fcvt h0, s0
+; CHECK-NOFP-GI-NEXT: ret
%b = call half @llvm.vector.reduce.fmax.v8f16(<8 x half> %a)
ret half %b
}
define half @test_v16f16(<16 x half> %a) nounwind {
-; CHECK-NOFP-LABEL: test_v16f16:
-; CHECK-NOFP: // %bb.0:
-; CHECK-NOFP-NEXT: mov h2, v1.h[1]
-; CHECK-NOFP-NEXT: mov h3, v0.h[1]
-; CHECK-NOFP-NEXT: fcvt s4, h1
-; CHECK-NOFP-NEXT: fcvt s5, h0
-; CHECK-NOFP-NEXT: fcvt s2, h2
-; CHECK-NOFP-NEXT: fcvt s3, h3
-; CHECK-NOFP-NEXT: fmaxnm s4, s5, s4
-; CHECK-NOFP-NEXT: mov h5, v0.h[2]
-; CHECK-NOFP-NEXT: fmaxnm s2, s3, s2
-; CHECK-NOFP-NEXT: mov h3, v1.h[2]
-; CHECK-NOFP-NEXT: fcvt h4, s4
-; CHECK-NOFP-NEXT: fcvt s5, h5
-; CHECK-NOFP-NEXT: fcvt h2, s2
-; CHECK-NOFP-NEXT: fcvt s3, h3
-; CHECK-NOFP-NEXT: fcvt s4, h4
-; CHECK-NOFP-NEXT: fcvt s2, h2
-; CHECK-NOFP-NEXT: fmaxnm s3, s5, s3
-; CHECK-NOFP-NEXT: mov h5, v0.h[3]
-; CHECK-NOFP-NEXT: fmaxnm s2, s4, s2
-; CHECK-NOFP-NEXT: mov h4, v1.h[3]
-; CHECK-NOFP-NEXT: fcvt h3, s3
-; CHECK-NOFP-NEXT: fcvt s5, h5
-; CHECK-NOFP-NEXT: fcvt h2, s2
-; CHECK-NOFP-NEXT: fcvt s4, h4
-; CHECK-NOFP-NEXT: fcvt s3, h3
-; CHECK-NOFP-NEXT: fcvt s2, h2
-; CHECK-NOFP-NEXT: fmaxnm s4, s5, s4
-; CHECK-NOFP-NEXT: mov h5, v0.h[4]
-; CHECK-NOFP-NEXT: fmaxnm s2, s2, s3
-; CHECK-NOFP-NEXT: mov h3, v1.h[4]
-; CHECK-NOFP-NEXT: fcvt h4, s4
-; CHECK-NOFP-NEXT: fcvt s5, h5
-; CHECK-NOFP-NEXT: fcvt h2, s2
-; CHECK-NOFP-NEXT: fcvt s3, h3
-; CHECK-NOFP-NEXT: fcvt s4, h4
-; CHECK-NOFP-NEXT: fcvt s2, h2
-; CHECK-NOFP-NEXT: fmaxnm s3, s5, s3
-; CHECK-NOFP-NEXT: mov h5, v0.h[5]
-; CHECK-NOFP-NEXT: fmaxnm s2, s2, s4
-; CHECK-NOFP-NEXT: mov h4, v1.h[5]
-; CHECK-NOFP-NEXT: fcvt h3, s3
-; CHECK-NOFP-NEXT: fcvt s5, h5
-; CHECK-NOFP-NEXT: fcvt h2, s2
-; CHECK-NOFP-NEXT: fcvt s4, h4
-; CHECK-NOFP-NEXT: fcvt s3, h3
-; CHECK-NOFP-NEXT: fcvt s2, h2
-; CHECK-NOFP-NEXT: fmaxnm s4, s5, s4
-; CHECK-NOFP-NEXT: mov h5, v0.h[6]
-; CHECK-NOFP-NEXT: mov h0, v0.h[7]
-; CHECK-NOFP-NEXT: fmaxnm s2, s2, s3
-; CHECK-NOFP-NEXT: mov h3, v1.h[6]
-; CHECK-NOFP-NEXT: fcvt h4, s4
-; CHECK-NOFP-NEXT: fcvt s5, h5
-; CHECK-NOFP-NEXT: mov h1, v1.h[7]
-; CHECK-NOFP-NEXT: fcvt s0, h0
-; CHECK-NOFP-NEXT: fcvt h2, s2
-; CHECK-NOFP-NEXT: fcvt s3, h3
-; CHECK-NOFP-NEXT: fcvt s4, h4
-; CHECK-NOFP-NEXT: fcvt s1, h1
-; CHECK-NOFP-NEXT: fcvt s2, h2
-; CHECK-NOFP-NEXT: fmaxnm s3, s5, s3
-; CHECK-NOFP-NEXT: fmaxnm s0, s0, s1
-; CHECK-NOFP-NEXT: fmaxnm s2, s2, s4
-; CHECK-NOFP-NEXT: fcvt h3, s3
-; CHECK-NOFP-NEXT: fcvt h0, s0
-; CHECK-NOFP-NEXT: fcvt h2, s2
-; CHECK-NOFP-NEXT: fcvt s3, h3
-; CHECK-NOFP-NEXT: fcvt s0, h0
-; CHECK-NOFP-NEXT: fcvt s2, h2
-; CHECK-NOFP-NEXT: fmaxnm s2, s2, s3
-; CHECK-NOFP-NEXT: fcvt h1, s2
-; CHECK-NOFP-NEXT: fcvt s1, h1
-; CHECK-NOFP-NEXT: fmaxnm s0, s1, s0
-; CHECK-NOFP-NEXT: fcvt h0, s0
-; CHECK-NOFP-NEXT: ret
+; CHECK-NOFP-SD-LABEL: test_v16f16:
+; CHECK-NOFP-SD: // %bb.0:
+; CHECK-NOFP-SD-NEXT: mov h2, v1.h[1]
+; CHECK-NOFP-SD-NEXT: mov h3, v0.h[1]
+; CHECK-NOFP-SD-NEXT: fcvt s4, h1
+; CHECK-NOFP-SD-NEXT: fcvt s5, h0
+; CHECK-NOFP-SD-NEXT: fcvt s2, h2
+; CHECK-NOFP-SD-NEXT: fcvt s3, h3
+; CHECK-NOFP-SD-NEXT: fmaxnm s4, s5, s4
+; CHECK-NOFP-SD-NEXT: mov h5, v0.h[2]
+; CHECK-NOFP-SD-NEXT: fmaxnm s2, s3, s2
+; CHECK-NOFP-SD-NEXT: mov h3, v1.h[2]
+; CHECK-NOFP-SD-NEXT: fcvt h4, s4
+; CHECK-NOFP-SD-NEXT: fcvt s5, h5
+; CHECK-NOFP-SD-NEXT: fcvt h2, s2
+; CHECK-NOFP-SD-NEXT: fcvt s3, h3
+; CHECK-NOFP-SD-NEXT: fcvt s4, h4
+; CHECK-NOFP-SD-NEXT: fcvt s2, h2
+; CHECK-NOFP-SD-NEXT: fmaxnm s3, s5, s3
+; CHECK-NOFP-SD-NEXT: mov h5, v0.h[3]
+; CHECK-NOFP-SD-NEXT: fmaxnm s2, s4, s2
+; CHECK-NOFP-SD-NEXT: mov h4, v1.h[3]
+; CHECK-NOFP-SD-NEXT: fcvt h3, s3
+; CHECK-NOFP-SD-NEXT: fcvt s5, h5
+; CHECK-NOFP-SD-NEXT: fcvt h2, s2
+; CHECK-NOFP-SD-NEXT: fcvt s4, h4
+; CHECK-NOFP-SD-NEXT: fcvt s3, h3
+; CHECK-NOFP-SD-NEXT: fcvt s2, h2
+; CHECK-NOFP-SD-NEXT: fmaxnm s4, s5, s4
+; CHECK-NOFP-SD-NEXT: mov h5, v0.h[4]
+; CHECK-NOFP-SD-NEXT: fmaxnm s2, s2, s3
+; CHECK-NOFP-SD-NEXT: mov h3, v1.h[4]
+; CHECK-NOFP-SD-NEXT: fcvt h4, s4
+; CHECK-NOFP-SD-NEXT: fcvt s5, h5
+; CHECK-NOFP-SD-NEXT: fcvt h2, s2
+; CHECK-NOFP-SD-NEXT: fcvt s3, h3
+; CHECK-NOFP-SD-NEXT: fcvt s4, h4
+; CHECK-NOFP-SD-NEXT: fcvt s2, h2
+; CHECK-NOFP-SD-NEXT: fmaxnm s3, s5, s3
+; CHECK-NOFP-SD-NEXT: mov h5, v0.h[5]
+; CHECK-NOFP-SD-NEXT: fmaxnm s2, s2, s4
+; CHECK-NOFP-SD-NEXT: mov h4, v1.h[5]
+; CHECK-NOFP-SD-NEXT: fcvt h3, s3
+; CHECK-NOFP-SD-NEXT: fcvt s5, h5
+; CHECK-NOFP-SD-NEXT: fcvt h2, s2
+; CHECK-NOFP-SD-NEXT: fcvt s4, h4
+; CHECK-NOFP-SD-NEXT: fcvt s3, h3
+; CHECK-NOFP-SD-NEXT: fcvt s2, h2
+; CHECK-NOFP-SD-NEXT: fmaxnm s4, s5, s4
+; CHECK-NOFP-SD-NEXT: mov h5, v0.h[6]
+; CHECK-NOFP-SD-NEXT: mov h0, v0.h[7]
+; CHECK-NOFP-SD-NEXT: fmaxnm s2, s2, s3
+; CHECK-NOFP-SD-NEXT: mov h3, v1.h[6]
+; CHECK-NOFP-SD-NEXT: fcvt h4, s4
+; CHECK-NOFP-SD-NEXT: fcvt s5, h5
+; CHECK-NOFP-SD-NEXT: mov h1, v1.h[7]
+; CHECK-NOFP-SD-NEXT: fcvt s0, h0
+; CHECK-NOFP-SD-NEXT: fcvt h2, s2
+; CHECK-NOFP-SD-NEXT: fcvt s3, h3
+; CHECK-NOFP-SD-NEXT: fcvt s4, h4
+; CHECK-NOFP-SD-NEXT: fcvt s1, h1
+; CHECK-NOFP-SD-NEXT: fcvt s2, h2
+; CHECK-NOFP-SD-NEXT: fmaxnm s3, s5, s3
+; CHECK-NOFP-SD-NEXT: fmaxnm s0, s0, s1
+; CHECK-NOFP-SD-NEXT: fmaxnm s2, s2, s4
+; CHECK-NOFP-SD-NEXT: fcvt h3, s3
+; CHECK-NOFP-SD-NEXT: fcvt h0, s0
+; CHECK-NOFP-SD-NEXT: fcvt h2, s2
+; CHECK-NOFP-SD-NEXT: fcvt s3, h3
+; CHECK-NOFP-SD-NEXT: fcvt s0, h0
+; CHECK-NOFP-SD-NEXT: fcvt s2, h2
+; CHECK-NOFP-SD-NEXT: fmaxnm s2, s2, s3
+; CHECK-NOFP-SD-NEXT: fcvt h1, s2
+; CHECK-NOFP-SD-NEXT: fcvt s1, h1
+; CHECK-NOFP-SD-NEXT: fmaxnm s0, s1, s0
+; CHECK-NOFP-SD-NEXT: fcvt h0, s0
+; CHECK-NOFP-SD-NEXT: ret
;
; CHECK-FP-LABEL: test_v16f16:
; CHECK-FP: // %bb.0:
; CHECK-FP-NEXT: fmaxnm v0.8h, v0.8h, v1.8h
; CHECK-FP-NEXT: fmaxnmv h0, v0.8h
; CHECK-FP-NEXT: ret
+;
+; CHECK-NOFP-GI-LABEL: test_v16f16:
+; CHECK-NOFP-GI: // %bb.0:
+; CHECK-NOFP-GI-NEXT: fcvtl v2.4s, v0.4h
+; CHECK-NOFP-GI-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-NOFP-GI-NEXT: fcvtl v3.4s, v1.4h
+; CHECK-NOFP-GI-NEXT: fcvtl2 v1.4s, v1.8h
+; CHECK-NOFP-GI-NEXT: fmaxnm v0.4s, v2.4s, v0.4s
+; CHECK-NOFP-GI-NEXT: fmaxnm v1.4s, v3.4s, v1.4s
+; CHECK-NOFP-GI-NEXT: fmaxnm v0.4s, v0.4s, v1.4s
+; CHECK-NOFP-GI-NEXT: fmaxnmv s0, v0.4s
+; CHECK-NOFP-GI-NEXT: fcvt h0, s0
+; CHECK-NOFP-GI-NEXT: ret
%b = call half @llvm.vector.reduce.fmax.v16f16(<16 x half> %a)
ret half %b
}
@@ -278,13 +346,37 @@ define float @test_v8f32(<8 x float> %a) nounwind {
}
define float @test_v16f32(<16 x float> %a) nounwind {
-; CHECK-LABEL: test_v16f32:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fmaxnm v1.4s, v1.4s, v3.4s
-; CHECK-NEXT: fmaxnm v0.4s, v0.4s, v2.4s
-; CHECK-NEXT: fmaxnm v0.4s, v0.4s, v1.4s
-; CHECK-NEXT: fmaxnmv s0, v0.4s
-; CHECK-NEXT: ret
+; CHECK-NOFP-SD-LABEL: test_v16f32:
+; CHECK-NOFP-SD: // %bb.0:
+; CHECK-NOFP-SD-NEXT: fmaxnm v1.4s, v1.4s, v3.4s
+; CHECK-NOFP-SD-NEXT: fmaxnm v0.4s, v0.4s, v2.4s
+; CHECK-NOFP-SD-NEXT: fmaxnm v0.4s, v0.4s, v1.4s
+; CHECK-NOFP-SD-NEXT: fmaxnmv s0, v0.4s
+; CHECK-NOFP-SD-NEXT: ret
+;
+; CHECK-FP-SD-LABEL: test_v16f32:
+; CHECK-FP-SD: // %bb.0:
+; CHECK-FP-SD-NEXT: fmaxnm v1.4s, v1.4s, v3.4s
+; CHECK-FP-SD-NEXT: fmaxnm v0.4s, v0.4s, v2.4s
+; CHECK-FP-SD-NEXT: fmaxnm v0.4s, v0.4s, v1.4s
+; CHECK-FP-SD-NEXT: fmaxnmv s0, v0.4s
+; CHECK-FP-SD-NEXT: ret
+;
+; CHECK-NOFP-GI-LABEL: test_v16f32:
+; CHECK-NOFP-GI: // %bb.0:
+; CHECK-NOFP-GI-NEXT: fmaxnm v0.4s, v0.4s, v1.4s
+; CHECK-NOFP-GI-NEXT: fmaxnm v1.4s, v2.4s, v3.4s
+; CHECK-NOFP-GI-NEXT: fmaxnm v0.4s, v0.4s, v1.4s
+; CHECK-NOFP-GI-NEXT: fmaxnmv s0, v0.4s
+; CHECK-NOFP-GI-NEXT: ret
+;
+; CHECK-FP-GI-LABEL: test_v16f32:
+; CHECK-FP-GI: // %bb.0:
+; CHECK-FP-GI-NEXT: fmaxnm v0.4s, v0.4s, v1.4s
+; CHECK-FP-GI-NEXT: fmaxnm v1.4s, v2.4s, v3.4s
+; CHECK-FP-GI-NEXT: fmaxnm v0.4s, v0.4s, v1.4s
+; CHECK-FP-GI-NEXT: fmaxnmv s0, v0.4s
+; CHECK-FP-GI-NEXT: ret
%b = call float @llvm.vector.reduce.fmax.v16f32(<16 x float> %a)
ret float %b
}
diff --git a/llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization.ll b/llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization.ll
index 9302681b709db8..067c766875c8ce 100644
--- a/llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization.ll
+++ b/llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization.ll
@@ -1,6 +1,20 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NOFP
-; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon,+fullfp16 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FP
+; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NOFP --check-prefix=CHECK-NOFP-SD
+; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon,+fullfp16 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FP --check-prefix=CHECK-FP-SD
+; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NOFP --check-prefix=CHECK-NOFP-GI
+; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon,+fullfp16 -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FP --check-prefix=CHECK-FP-GI
+
+; CHECK-NOFP-GI: warning: Instruction selection used fallback path for test_v11f16
+; CHECK-NOFP-GI-NEXT: warning: Instruction selection used fallback path for test_v11f16_ninf
+; CHECK-NOFP-GI-NEXT: warning: Instruction selection used fallback path for test_v3f32
+; CHECK-NOFP-GI-NEXT: warning: Instruction selection used fallback path for test_v3f32_ninf
+; CHECK-NOFP-GI-NEXT: warning: Instruction selection used fallback path for test_v2f128
+;
+; CHECK-FP-GI: warning: Instruction selection used fallback path for test_v11f16
+; CHECK-FP-GI-NEXT: warning: Instruction selection used fallback path for test_v11f16_ninf
+; CHECK-FP-GI-NEXT: warning: Instruction selection used fallback path for test_v3f32
+; CHECK-FP-GI-NEXT: warning: Instruction selection used fallback path for test_v3f32_ninf
+; CHECK-FP-GI-NEXT: warning: Instruction selection used fallback path for test_v2f128
declare half @llvm.vector.reduce.fmax.v1f16(<1 x half> %a)
declare float @llvm.vector.reduce.fmax.v1f32(<1 x float> %a)
@@ -30,11 +44,29 @@ define half @test_v1f16(<1 x half> %a) nounwind {
}
define float @test_v1f32(<1 x float> %a) nounwind {
-; CHECK-LABEL: test_v1f32:
-; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
-; CHECK-NEXT: ret
+; CHECK-NOFP-SD-LABEL: test_v1f32:
+; CHECK-NOFP-SD: // %bb.0:
+; CHECK-NOFP-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NOFP-SD-NEXT: // kill: def $s0 killed $s0 killed $q0
+; CHECK-NOFP-SD-NEXT: ret
+;
+; CHECK-FP-SD-LABEL: test_v1f32:
+; CHECK-FP-SD: // %bb.0:
+; CHECK-FP-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP-SD-NEXT: // kill: def $s0 killed $s0 killed $q0
+; CHECK-FP-SD-NEXT: ret
+;
+; CHECK-NOFP-GI-LABEL: test_v1f32:
+; CHECK-NOFP-GI: // %bb.0:
+; CHECK-NOFP-GI-NEXT: fmov x8, d0
+; CHECK-NOFP-GI-NEXT: fmov s0, w8
+; CHECK-NOFP-GI-NEXT: ret
+;
+; CHECK-FP-GI-LABEL: test_v1f32:
+; CHECK-FP-GI: // %bb.0:
+; CHECK-FP-GI-NEXT: fmov x8, d0
+; CHECK-FP-GI-NEXT: fmov s0, w8
+; CHECK-FP-GI-NEXT: ret
%b = call nnan float @llvm.vector.reduce.fmax.v1f32(<1 x float> %a)
ret float %b
}
@@ -56,203 +88,239 @@ define fp128 @test_v1f128(<1 x fp128> %a) nounwind {
}
define half @test_v4f16(<4 x half> %a) nounwind {
-; CHECK-NOFP-LABEL: test_v4f16:
-; CHECK-NOFP: // %bb.0:
-; CHECK-NOFP-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NOFP-NEXT: mov h1, v0.h[1]
-; CHECK-NOFP-NEXT: fcvt s2, h0
-; CHECK-NOFP-NEXT: fcvt s1, h1
-; CHECK-NOFP-NEXT: fmaxnm s1, s2, s1
-; CHECK-NOFP-NEXT: mov h2, v0.h[2]
-; CHECK-NOFP-NEXT: mov h0, v0.h[3]
-; CHECK-NOFP-NEXT: fcvt h1, s1
-; CHECK-NOFP-NEXT: fcvt s2, h2
-; CHECK-NOFP-NEXT: fcvt s0, h0
-; CHECK-NOFP-NEXT: fcvt s1, h1
-; CHECK-NOFP-NEXT: fmaxnm s1, s1, s2
-; CHECK-NOFP-NEXT: fcvt h1, s1
-; CHECK-NOFP-NEXT: fcvt s1, h1
-; CHECK-NOFP-NEXT: fmaxnm s0, s1, s0
-; CHECK-NOFP-NEXT: fcvt h0, s0
-; CHECK-NOFP-NEXT: ret
+; CHECK-NOFP-SD-LABEL: test_v4f16:
+; CHECK-NOFP-SD: // %bb.0:
+; CHECK-NOFP-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NOFP-SD-NEXT: mov h1, v0.h[1]
+; CHECK-NOFP-SD-NEXT: fcvt s2, h0
+; CHECK-NOFP-SD-NEXT: fcvt s1, h1
+; CHECK-NOFP-SD-NEXT: fmaxnm s1, s2, s1
+; CHECK-NOFP-SD-NEXT: mov h2, v0.h[2]
+; CHECK-NOFP-SD-NEXT: mov h0, v0.h[3]
+; CHECK-NOFP-SD-NEXT: fcvt h1, s1
+; CHECK-NOFP-SD-NEXT: fcvt s2, h2
+; CHECK-NOFP-SD-NEXT: fcvt s0, h0
+; CHECK-NOFP-SD-NEXT: fcvt s1, h1
+; CHECK-NOFP-SD-NEXT: fmaxnm s1, s1, s2
+; CHECK-NOFP-SD-NEXT: fcvt h1, s1
+; CHECK-NOFP-SD-NEXT: fcvt s1, h1
+; CHECK-NOFP-SD-NEXT: fmaxnm s0, s1, s0
+; CHECK-NOFP-SD-NEXT: fcvt h0, s0
+; CHECK-NOFP-SD-NEXT: ret
;
; CHECK-FP-LABEL: test_v4f16:
; CHECK-FP: // %bb.0:
; CHECK-FP-NEXT: fmaxnmv h0, v0.4h
; CHECK-FP-NEXT: ret
+;
+; CHECK-NOFP-GI-LABEL: test_v4f16:
+; CHECK-NOFP-GI: // %bb.0:
+; CHECK-NOFP-GI-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-NOFP-GI-NEXT: fmaxnmv s0, v0.4s
+; CHECK-NOFP-GI-NEXT: fcvt h0, s0
+; CHECK-NOFP-GI-NEXT: ret
%b = call nnan half @llvm.vector.reduce.fmax.v4f16(<4 x half> %a)
ret half %b
}
define half @test_v4f16_ninf(<4 x half> %a) nounwind {
-; CHECK-NOFP-LABEL: test_v4f16_ninf:
-; CHECK-NOFP: // %bb.0:
-; CHECK-NOFP-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NOFP-NEXT: mov h1, v0.h[1]
-; CHECK-NOFP-NEXT: fcvt s2, h0
-; CHECK-NOFP-NEXT: fcvt s1, h1
-; CHECK-NOFP-NEXT: fmaxnm s1, s2, s1
-; CHECK-NOFP-NEXT: mov h2, v0.h[2]
-; CHECK-NOFP-NEXT: mov h0, v0.h[3]
-; CHECK-NOFP-NEXT: fcvt h1, s1
-; CHECK-NOFP-NEXT: fcvt s2, h2
-; CHECK-NOFP-NEXT: fcvt s0, h0
-; CHECK-NOFP-NEXT: fcvt s1, h1
-; CHECK-NOFP-NEXT: fmaxnm s1, s1, s2
-; CHECK-NOFP-NEXT: fcvt h1, s1
-; CHECK-NOFP-NEXT: fcvt s1, h1
-; CHECK-NOFP-NEXT: fmaxnm s0, s1, s0
-; CHECK-NOFP-NEXT: fcvt h0, s0
-; CHECK-NOFP-NEXT: ret
+; CHECK-NOFP-SD-LABEL: test_v4f16_ninf:
+; CHECK-NOFP-SD: // %bb.0:
+; CHECK-NOFP-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NOFP-SD-NEXT: mov h1, v0.h[1]
+; CHECK-NOFP-SD-NEXT: fcvt s2, h0
+; CHECK-NOFP-SD-NEXT: fcvt s1, h1
+; CHECK-NOFP-SD-NEXT: fmaxnm s1, s2, s1
+; CHECK-NOFP-SD-NEXT: mov h2, v0.h[2]
+; CHECK-NOFP-SD-NEXT: mov h0, v0.h[3]
+; CHECK-NOFP-SD-NEXT: fcvt h1, s1
+; CHECK-NOFP-SD-NEXT: fcvt s2, h2
+; CHECK-NOFP-SD-NEXT: fcvt s0, h0
+; CHECK-NOFP-SD-NEXT: fcvt s1, h1
+; CHECK-NOFP-SD-NEXT: fmaxnm s1, s1, s2
+; CHECK-NOFP-SD-NEXT: fcvt h1, s1
+; CHECK-NOFP-SD-NEXT: fcvt s1, h1
+; CHECK-NOFP-SD-NEXT: fmaxnm s0, s1, s0
+; CHECK-NOFP-SD-NEXT: fcvt h0, s0
+; CHECK-NOFP-SD-NEXT: ret
;
; CHECK-FP-LABEL: test_v4f16_ninf:
; CHECK-FP: // %bb.0:
; CHECK-FP-NEXT: fmaxnmv h0, v0.4h
; CHECK-FP-NEXT: ret
+;
+; CHECK-NOFP-GI-LABEL: test_v4f16_ninf:
+; CHECK-NOFP-GI: // %bb.0:
+; CHECK-NOFP-GI-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-NOFP-GI-NEXT: fmaxnmv s0, v0.4s
+; CHECK-NOFP-GI-NEXT: fcvt h0, s0
+; CHECK-NOFP-GI-NEXT: ret
%b = call nnan ninf half @llvm.vector.reduce.fmax.v4f16(<4 x half> %a)
ret half %b
}
define half @test_v8f16(<8 x half> %a) nounwind {
-; CHECK-NOFP-LABEL: test_v8f16:
-; CHECK-NOFP: // %bb.0:
-; CHECK-NOFP-NEXT: mov h1, v0.h[1]
-; CHECK-NOFP-NEXT: fcvt s2, h0
-; CHECK-NOFP-NEXT: fcvt s1, h1
-; CHECK-NOFP-NEXT: fmaxnm s1, s2, s1
-; CHECK-NOFP-NEXT: mov h2, v0.h[2]
-; CHECK-NOFP-NEXT: fcvt h1, s1
-; CHECK-NOFP-NEXT: fcvt s2, h2
-; CHECK-NOFP-NEXT: fcvt s1, h1
-; CHECK-NOFP-NEXT: fmaxnm s1, s1, s2
-; CHECK-NOFP-NEXT: mov h2, v0.h[3]
-; CHECK-NOFP-NEXT: fcvt h1, s1
-; CHECK-NOFP-NEXT: fcvt s2, h2
-; CHECK-NOFP-NEXT: fcvt s1, h1
-; CHECK-NOFP-NEXT: fmaxnm s1, s1, s2
-; CHECK-NOFP-NEXT: mov h2, v0.h[4]
-; CHECK-NOFP-NEXT: fcvt h1, s1
-; CHECK-NOFP-NEXT: fcvt s2, h2
-; CHECK-NOFP-NEXT: fcvt s1, h1
-; CHECK-NOFP-NEXT: fmaxnm s1, s1, s2
-; CHECK-NOFP-NEXT: mov h2, v0.h[5]
-; CHECK-NOFP-NEXT: fcvt h1, s1
-; CHECK-NOFP-NEXT: fcvt s2, h2
-; CHECK-NOFP-NEXT: fcvt s1, h1
-; CHECK-NOFP-NEXT: fmaxnm s1, s1, s2
-; CHECK-NOFP-NEXT: mov h2, v0.h[6]
-; CHECK-NOFP-NEXT: mov h0, v0.h[7]
-; CHECK-NOFP-NEXT: fcvt h1, s1
-; CHECK-NOFP-NEXT: fcvt s2, h2
-; CHECK-NOFP-NEXT: fcvt s0, h0
-; CHECK-NOFP-NEXT: fcvt s1, h1
-; CHECK-NOFP-NEXT: fmaxnm s1, s1, s2
-; CHECK-NOFP-NEXT: fcvt h1, s1
-; CHECK-NOFP-NEXT: fcvt s1, h1
-; CHECK-NOFP-NEXT: fmaxnm s0, s1, s0
-; CHECK-NOFP-NEXT: fcvt h0, s0
-; CHECK-NOFP-NEXT: ret
+; CHECK-NOFP-SD-LABEL: test_v8f16:
+; CHECK-NOFP-SD: // %bb.0:
+; CHECK-NOFP-SD-NEXT: mov h1, v0.h[1]
+; CHECK-NOFP-SD-NEXT: fcvt s2, h0
+; CHECK-NOFP-SD-NEXT: fcvt s1, h1
+; CHECK-NOFP-SD-NEXT: fmaxnm s1, s2, s1
+; CHECK-NOFP-SD-NEXT: mov h2, v0.h[2]
+; CHECK-NOFP-SD-NEXT: fcvt h1, s1
+; CHECK-NOFP-SD-NEXT: fcvt s2, h2
+; CHECK-NOFP-SD-NEXT: fcvt s1, h1
+; CHECK-NOFP-SD-NEXT: fmaxnm s1, s1, s2
+; CHECK-NOFP-SD-NEXT: mov h2, v0.h[3]
+; CHECK-NOFP-SD-NEXT: fcvt h1, s1
+; CHECK-NOFP-SD-NEXT: fcvt s2, h2
+; CHECK-NOFP-SD-NEXT: fcvt s1, h1
+; CHECK-NOFP-SD-NEXT: fmaxnm s1, s1, s2
+; CHECK-NOFP-SD-NEXT: mov h2, v0.h[4]
+; CHECK-NOFP-SD-NEXT: fcvt h1, s1
+; CHECK-NOFP-SD-NEXT: fcvt s2, h2
+; CHECK-NOFP-SD-NEXT: fcvt s1, h1
+; CHECK-NOFP-SD-NEXT: fmaxnm s1, s1, s2
+; CHECK-NOFP-SD-NEXT: mov h2, v0.h[5]
+; CHECK-NOFP-SD-NEXT: fcvt h1, s1
+; CHECK-NOFP-SD-NEXT: fcvt s2, h2
+; CHECK-NOFP-SD-NEXT: fcvt s1, h1
+; CHECK-NOFP-SD-NEXT: fmaxnm s1, s1, s2
+; CHECK-NOFP-SD-NEXT: mov h2, v0.h[6]
+; CHECK-NOFP-SD-NEXT: mov h0, v0.h[7]
+; CHECK-NOFP-SD-NEXT: fcvt h1, s1
+; CHECK-NOFP-SD-NEXT: fcvt s2, h2
+; CHECK-NOFP-SD-NEXT: fcvt s0, h0
+; CHECK-NOFP-SD-NEXT: fcvt s1, h1
+; CHECK-NOFP-SD-NEXT: fmaxnm s1, s1, s2
+; CHECK-NOFP-SD-NEXT: fcvt h1, s1
+; CHECK-NOFP-SD-NEXT: fcvt s1, h1
+; CHECK-NOFP-SD-NEXT: fmaxnm s0, s1, s0
+; CHECK-NOFP-SD-NEXT: fcvt h0, s0
+; CHECK-NOFP-SD-NEXT: ret
;
; CHECK-FP-LABEL: test_v8f16:
; CHECK-FP: // %bb.0:
; CHECK-FP-NEXT: fmaxnmv h0, v0.8h
; CHECK-FP-NEXT: ret
+;
+; CHECK-NOFP-GI-LABEL: test_v8f16:
+; CHECK-NOFP-GI: // %bb.0:
+; CHECK-NOFP-GI-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-NOFP-GI-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-NOFP-GI-NEXT: fmaxnm v0.4s, v1.4s, v0.4s
+; CHECK-NOFP-GI-NEXT: fmaxnmv s0, v0.4s
+; CHECK-NOFP-GI-NEXT: fcvt h0, s0
+; CHECK-NOFP-GI-NEXT: ret
%b = call nnan half @llvm.vector.reduce.fmax.v8f16(<8 x half> %a)
ret half %b
}
define half @test_v16f16(<16 x half> %a) nounwind {
-; CHECK-NOFP-LABEL: test_v16f16:
-; CHECK-NOFP: // %bb.0:
-; CHECK-NOFP-NEXT: mov h2, v1.h[1]
-; CHECK-NOFP-NEXT: mov h3, v0.h[1]
-; CHECK-NOFP-NEXT: fcvt s4, h1
-; CHECK-NOFP-NEXT: fcvt s5, h0
-; CHECK-NOFP-NEXT: fcvt s2, h2
-; CHECK-NOFP-NEXT: fcvt s3, h3
-; CHECK-NOFP-NEXT: fcmp s3, s2
-; CHECK-NOFP-NEXT: fcsel s2, s3, s2, gt
-; CHECK-NOFP-NEXT: fcmp s5, s4
-; CHECK-NOFP-NEXT: fcsel s3, s5, s4, gt
-; CHECK-NOFP-NEXT: mov h4, v1.h[2]
-; CHECK-NOFP-NEXT: mov h5, v0.h[2]
-; CHECK-NOFP-NEXT: fcvt h2, s2
-; CHECK-NOFP-NEXT: fcvt h3, s3
-; CHECK-NOFP-NEXT: fcvt s4, h4
-; CHECK-NOFP-NEXT: fcvt s5, h5
-; CHECK-NOFP-NEXT: fcvt s2, h2
-; CHECK-NOFP-NEXT: fcvt s3, h3
-; CHECK-NOFP-NEXT: fcmp s5, s4
-; CHECK-NOFP-NEXT: fmaxnm s2, s3, s2
-; CHECK-NOFP-NEXT: fcsel s3, s5, s4, gt
-; CHECK-NOFP-NEXT: mov h4, v1.h[3]
-; CHECK-NOFP-NEXT: mov h5, v0.h[3]
-; CHECK-NOFP-NEXT: fcvt h2, s2
-; CHECK-NOFP-NEXT: fcvt h3, s3
-; CHECK-NOFP-NEXT: fcvt s4, h4
-; CHECK-NOFP-NEXT: fcvt s5, h5
-; CHECK-NOFP-NEXT: fcvt s2, h2
-; CHECK-NOFP-NEXT: fcvt s3, h3
-; CHECK-NOFP-NEXT: fcmp s5, s4
-; CHECK-NOFP-NEXT: fmaxnm s2, s2, s3
-; CHECK-NOFP-NEXT: fcsel s3, s5, s4, gt
-; CHECK-NOFP-NEXT: mov h4, v1.h[4]
-; CHECK-NOFP-NEXT: mov h5, v0.h[4]
-; CHECK-NOFP-NEXT: fcvt h2, s2
-; CHECK-NOFP-NEXT: fcvt h3, s3
-; CHECK-NOFP-NEXT: fcvt s4, h4
-; CHECK-NOFP-NEXT: fcvt s5, h5
-; CHECK-NOFP-NEXT: fcvt s2, h2
-; CHECK-NOFP-NEXT: fcvt s3, h3
-; CHECK-NOFP-NEXT: fcmp s5, s4
-; CHECK-NOFP-NEXT: fmaxnm s2, s2, s3
-; CHECK-NOFP-NEXT: fcsel s3, s5, s4, gt
-; CHECK-NOFP-NEXT: mov h4, v1.h[5]
-; CHECK-NOFP-NEXT: mov h5, v0.h[5]
-; CHECK-NOFP-NEXT: fcvt h2, s2
-; CHECK-NOFP-NEXT: fcvt h3, s3
-; CHECK-NOFP-NEXT: fcvt s4, h4
-; CHECK-NOFP-NEXT: fcvt s5, h5
-; CHECK-NOFP-NEXT: fcvt s2, h2
-; CHECK-NOFP-NEXT: fcvt s3, h3
-; CHECK-NOFP-NEXT: fcmp s5, s4
-; CHECK-NOFP-NEXT: fmaxnm s2, s2, s3
-; CHECK-NOFP-NEXT: fcsel s3, s5, s4, gt
-; CHECK-NOFP-NEXT: mov h4, v1.h[6]
-; CHECK-NOFP-NEXT: mov h5, v0.h[6]
-; CHECK-NOFP-NEXT: mov h1, v1.h[7]
-; CHECK-NOFP-NEXT: mov h0, v0.h[7]
-; CHECK-NOFP-NEXT: fcvt h2, s2
-; CHECK-NOFP-NEXT: fcvt h3, s3
-; CHECK-NOFP-NEXT: fcvt s4, h4
-; CHECK-NOFP-NEXT: fcvt s5, h5
-; CHECK-NOFP-NEXT: fcvt s1, h1
-; CHECK-NOFP-NEXT: fcvt s0, h0
-; CHECK-NOFP-NEXT: fcvt s2, h2
-; CHECK-NOFP-NEXT: fcvt s3, h3
-; CHECK-NOFP-NEXT: fcmp s5, s4
-; CHECK-NOFP-NEXT: fmaxnm s2, s2, s3
-; CHECK-NOFP-NEXT: fcsel s3, s5, s4, gt
-; CHECK-NOFP-NEXT: fcmp s0, s1
-; CHECK-NOFP-NEXT: fcvt h2, s2
-; CHECK-NOFP-NEXT: fcvt h3, s3
-; CHECK-NOFP-NEXT: fcsel s0, s0, s1, gt
-; CHECK-NOFP-NEXT: fcvt s2, h2
-; CHECK-NOFP-NEXT: fcvt s3, h3
-; CHECK-NOFP-NEXT: fcvt h0, s0
-; CHECK-NOFP-NEXT: fmaxnm s2, s2, s3
-; CHECK-NOFP-NEXT: fcvt s0, h0
-; CHECK-NOFP-NEXT: fcvt h1, s2
-; CHECK-NOFP-NEXT: fcvt s1, h1
-; CHECK-NOFP-NEXT: fmaxnm s0, s1, s0
-; CHECK-NOFP-NEXT: fcvt h0, s0
-; CHECK-NOFP-NEXT: ret
+; CHECK-NOFP-SD-LABEL: test_v16f16:
+; CHECK-NOFP-SD: // %bb.0:
+; CHECK-NOFP-SD-NEXT: mov h2, v1.h[1]
+; CHECK-NOFP-SD-NEXT: mov h3, v0.h[1]
+; CHECK-NOFP-SD-NEXT: fcvt s4, h1
+; CHECK-NOFP-SD-NEXT: fcvt s5, h0
+; CHECK-NOFP-SD-NEXT: fcvt s2, h2
+; CHECK-NOFP-SD-NEXT: fcvt s3, h3
+; CHECK-NOFP-SD-NEXT: fcmp s3, s2
+; CHECK-NOFP-SD-NEXT: fcsel s2, s3, s2, gt
+; CHECK-NOFP-SD-NEXT: fcmp s5, s4
+; CHECK-NOFP-SD-NEXT: fcsel s3, s5, s4, gt
+; CHECK-NOFP-SD-NEXT: mov h4, v1.h[2]
+; CHECK-NOFP-SD-NEXT: mov h5, v0.h[2]
+; CHECK-NOFP-SD-NEXT: fcvt h2, s2
+; CHECK-NOFP-SD-NEXT: fcvt h3, s3
+; CHECK-NOFP-SD-NEXT: fcvt s4, h4
+; CHECK-NOFP-SD-NEXT: fcvt s5, h5
+; CHECK-NOFP-SD-NEXT: fcvt s2, h2
+; CHECK-NOFP-SD-NEXT: fcvt s3, h3
+; CHECK-NOFP-SD-NEXT: fcmp s5, s4
+; CHECK-NOFP-SD-NEXT: fmaxnm s2, s3, s2
+; CHECK-NOFP-SD-NEXT: fcsel s3, s5, s4, gt
+; CHECK-NOFP-SD-NEXT: mov h4, v1.h[3]
+; CHECK-NOFP-SD-NEXT: mov h5, v0.h[3]
+; CHECK-NOFP-SD-NEXT: fcvt h2, s2
+; CHECK-NOFP-SD-NEXT: fcvt h3, s3
+; CHECK-NOFP-SD-NEXT: fcvt s4, h4
+; CHECK-NOFP-SD-NEXT: fcvt s5, h5
+; CHECK-NOFP-SD-NEXT: fcvt s2, h2
+; CHECK-NOFP-SD-NEXT: fcvt s3, h3
+; CHECK-NOFP-SD-NEXT: fcmp s5, s4
+; CHECK-NOFP-SD-NEXT: fmaxnm s2, s2, s3
+; CHECK-NOFP-SD-NEXT: fcsel s3, s5, s4, gt
+; CHECK-NOFP-SD-NEXT: mov h4, v1.h[4]
+; CHECK-NOFP-SD-NEXT: mov h5, v0.h[4]
+; CHECK-NOFP-SD-NEXT: fcvt h2, s2
+; CHECK-NOFP-SD-NEXT: fcvt h3, s3
+; CHECK-NOFP-SD-NEXT: fcvt s4, h4
+; CHECK-NOFP-SD-NEXT: fcvt s5, h5
+; CHECK-NOFP-SD-NEXT: fcvt s2, h2
+; CHECK-NOFP-SD-NEXT: fcvt s3, h3
+; CHECK-NOFP-SD-NEXT: fcmp s5, s4
+; CHECK-NOFP-SD-NEXT: fmaxnm s2, s2, s3
+; CHECK-NOFP-SD-NEXT: fcsel s3, s5, s4, gt
+; CHECK-NOFP-SD-NEXT: mov h4, v1.h[5]
+; CHECK-NOFP-SD-NEXT: mov h5, v0.h[5]
+; CHECK-NOFP-SD-NEXT: fcvt h2, s2
+; CHECK-NOFP-SD-NEXT: fcvt h3, s3
+; CHECK-NOFP-SD-NEXT: fcvt s4, h4
+; CHECK-NOFP-SD-NEXT: fcvt s5, h5
+; CHECK-NOFP-SD-NEXT: fcvt s2, h2
+; CHECK-NOFP-SD-NEXT: fcvt s3, h3
+; CHECK-NOFP-SD-NEXT: fcmp s5, s4
+; CHECK-NOFP-SD-NEXT: fmaxnm s2, s2, s3
+; CHECK-NOFP-SD-NEXT: fcsel s3, s5, s4, gt
+; CHECK-NOFP-SD-NEXT: mov h4, v1.h[6]
+; CHECK-NOFP-SD-NEXT: mov h5, v0.h[6]
+; CHECK-NOFP-SD-NEXT: mov h1, v1.h[7]
+; CHECK-NOFP-SD-NEXT: mov h0, v0.h[7]
+; CHECK-NOFP-SD-NEXT: fcvt h2, s2
+; CHECK-NOFP-SD-NEXT: fcvt h3, s3
+; CHECK-NOFP-SD-NEXT: fcvt s4, h4
+; CHECK-NOFP-SD-NEXT: fcvt s5, h5
+; CHECK-NOFP-SD-NEXT: fcvt s1, h1
+; CHECK-NOFP-SD-NEXT: fcvt s0, h0
+; CHECK-NOFP-SD-NEXT: fcvt s2, h2
+; CHECK-NOFP-SD-NEXT: fcvt s3, h3
+; CHECK-NOFP-SD-NEXT: fcmp s5, s4
+; CHECK-NOFP-SD-NEXT: fmaxnm s2, s2, s3
+; CHECK-NOFP-SD-NEXT: fcsel s3, s5, s4, gt
+; CHECK-NOFP-SD-NEXT: fcmp s0, s1
+; CHECK-NOFP-SD-NEXT: fcvt h2, s2
+; CHECK-NOFP-SD-NEXT: fcvt h3, s3
+; CHECK-NOFP-SD-NEXT: fcsel s0, s0, s1, gt
+; CHECK-NOFP-SD-NEXT: fcvt s2, h2
+; CHECK-NOFP-SD-NEXT: fcvt s3, h3
+; CHECK-NOFP-SD-NEXT: fcvt h0, s0
+; CHECK-NOFP-SD-NEXT: fmaxnm s2, s2, s3
+; CHECK-NOFP-SD-NEXT: fcvt s0, h0
+; CHECK-NOFP-SD-NEXT: fcvt h1, s2
+; CHECK-NOFP-SD-NEXT: fcvt s1, h1
+; CHECK-NOFP-SD-NEXT: fmaxnm s0, s1, s0
+; CHECK-NOFP-SD-NEXT: fcvt h0, s0
+; CHECK-NOFP-SD-NEXT: ret
;
; CHECK-FP-LABEL: test_v16f16:
; CHECK-FP: // %bb.0:
; CHECK-FP-NEXT: fmaxnm v0.8h, v0.8h, v1.8h
; CHECK-FP-NEXT: fmaxnmv h0, v0.8h
; CHECK-FP-NEXT: ret
+;
+; CHECK-NOFP-GI-LABEL: test_v16f16:
+; CHECK-NOFP-GI: // %bb.0:
+; CHECK-NOFP-GI-NEXT: fcvtl v2.4s, v0.4h
+; CHECK-NOFP-GI-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-NOFP-GI-NEXT: fcvtl v3.4s, v1.4h
+; CHECK-NOFP-GI-NEXT: fcvtl2 v1.4s, v1.8h
+; CHECK-NOFP-GI-NEXT: fmaxnm v0.4s, v2.4s, v0.4s
+; CHECK-NOFP-GI-NEXT: fmaxnm v1.4s, v3.4s, v1.4s
+; CHECK-NOFP-GI-NEXT: fmaxnm v0.4s, v0.4s, v1.4s
+; CHECK-NOFP-GI-NEXT: fmaxnmv s0, v0.4s
+; CHECK-NOFP-GI-NEXT: fcvt h0, s0
+; CHECK-NOFP-GI-NEXT: ret
%b = call nnan half @llvm.vector.reduce.fmax.v16f16(<16 x half> %a)
ret half %b
}
@@ -286,13 +354,37 @@ define float @test_v8f32(<8 x float> %a) nounwind {
}
define float @test_v16f32(<16 x float> %a) nounwind {
-; CHECK-LABEL: test_v16f32:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fmaxnm v1.4s, v1.4s, v3.4s
-; CHECK-NEXT: fmaxnm v0.4s, v0.4s, v2.4s
-; CHECK-NEXT: fmaxnm v0.4s, v0.4s, v1.4s
-; CHECK-NEXT: fmaxnmv s0, v0.4s
-; CHECK-NEXT: ret
+; CHECK-NOFP-SD-LABEL: test_v16f32:
+; CHECK-NOFP-SD: // %bb.0:
+; CHECK-NOFP-SD-NEXT: fmaxnm v1.4s, v1.4s, v3.4s
+; CHECK-NOFP-SD-NEXT: fmaxnm v0.4s, v0.4s, v2.4s
+; CHECK-NOFP-SD-NEXT: fmaxnm v0.4s, v0.4s, v1.4s
+; CHECK-NOFP-SD-NEXT: fmaxnmv s0, v0.4s
+; CHECK-NOFP-SD-NEXT: ret
+;
+; CHECK-FP-SD-LABEL: test_v16f32:
+; CHECK-FP-SD: // %bb.0:
+; CHECK-FP-SD-NEXT: fmaxnm v1.4s, v1.4s, v3.4s
+; CHECK-FP-SD-NEXT: fmaxnm v0.4s, v0.4s, v2.4s
+; CHECK-FP-SD-NEXT: fmaxnm v0.4s, v0.4s, v1.4s
+; CHECK-FP-SD-NEXT: fmaxnmv s0, v0.4s
+; CHECK-FP-SD-NEXT: ret
+;
+; CHECK-NOFP-GI-LABEL: test_v16f32:
+; CHECK-NOFP-GI: // %bb.0:
+; CHECK-NOFP-GI-NEXT: fmaxnm v0.4s, v0.4s, v1.4s
+; CHECK-NOFP-GI-NEXT: fmaxnm v1.4s, v2.4s, v3.4s
+; CHECK-NOFP-GI-NEXT: fmaxnm v0.4s, v0.4s, v1.4s
+; CHECK-NOFP-GI-NEXT: fmaxnmv s0, v0.4s
+; CHECK-NOFP-GI-NEXT: ret
+;
+; CHECK-FP-GI-LABEL: test_v16f32:
+; CHECK-FP-GI: // %bb.0:
+; CHECK-FP-GI-NEXT: fmaxnm v0.4s, v0.4s, v1.4s
+; CHECK-FP-GI-NEXT: fmaxnm v1.4s, v2.4s, v3.4s
+; CHECK-FP-GI-NEXT: fmaxnm v0.4s, v0.4s, v1.4s
+; CHECK-FP-GI-NEXT: fmaxnmv s0, v0.4s
+; CHECK-FP-GI-NEXT: ret
%b = call nnan float @llvm.vector.reduce.fmax.v16f32(<16 x float> %a)
ret float %b
}
diff --git a/llvm/test/CodeGen/AArch64/vecreduce-fmin-legalization.ll b/llvm/test/CodeGen/AArch64/vecreduce-fmin-legalization.ll
index 6817047b232f1f..3d73569ef1f44f 100644
--- a/llvm/test/CodeGen/AArch64/vecreduce-fmin-legalization.ll
+++ b/llvm/test/CodeGen/AArch64/vecreduce-fmin-legalization.ll
@@ -1,6 +1,20 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NOFP
-; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon,+fullfp16 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FP
+; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NOFP --check-prefix=CHECK-NOFP-SD
+; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon,+fullfp16 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FP --check-prefix=CHECK-FP-SD
+; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NOFP --check-prefix=CHECK-NOFP-GI
+; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon,+fullfp16 -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FP --check-prefix=CHECK-FP-GI
+
+; CHECK-NOFP-GI: warning: Instruction selection used fallback path for test_v11f16
+; CHECK-NOFP-GI-NEXT: warning: Instruction selection used fallback path for test_v11f16_ninf
+; CHECK-NOFP-GI-NEXT: warning: Instruction selection used fallback path for test_v3f32
+; CHECK-NOFP-GI-NEXT: warning: Instruction selection used fallback path for test_v3f32_ninf
+; CHECK-NOFP-GI-NEXT: warning: Instruction selection used fallback path for test_v2f128
+;
+; CHECK-FP-GI: warning: Instruction selection used fallback path for test_v11f16
+; CHECK-FP-GI-NEXT: warning: Instruction selection used fallback path for test_v11f16_ninf
+; CHECK-FP-GI-NEXT: warning: Instruction selection used fallback path for test_v3f32
+; CHECK-FP-GI-NEXT: warning: Instruction selection used fallback path for test_v3f32_ninf
+; CHECK-FP-GI-NEXT: warning: Instruction selection used fallback path for test_v2f128
declare half @llvm.vector.reduce.fmin.v1f16(<1 x half> %a)
declare float @llvm.vector.reduce.fmin.v1f32(<1 x float> %a)
@@ -30,11 +44,29 @@ define half @test_v1f16(<1 x half> %a) nounwind {
}
define float @test_v1f32(<1 x float> %a) nounwind {
-; CHECK-LABEL: test_v1f32:
-; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
-; CHECK-NEXT: ret
+; CHECK-NOFP-SD-LABEL: test_v1f32:
+; CHECK-NOFP-SD: // %bb.0:
+; CHECK-NOFP-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NOFP-SD-NEXT: // kill: def $s0 killed $s0 killed $q0
+; CHECK-NOFP-SD-NEXT: ret
+;
+; CHECK-FP-SD-LABEL: test_v1f32:
+; CHECK-FP-SD: // %bb.0:
+; CHECK-FP-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP-SD-NEXT: // kill: def $s0 killed $s0 killed $q0
+; CHECK-FP-SD-NEXT: ret
+;
+; CHECK-NOFP-GI-LABEL: test_v1f32:
+; CHECK-NOFP-GI: // %bb.0:
+; CHECK-NOFP-GI-NEXT: fmov x8, d0
+; CHECK-NOFP-GI-NEXT: fmov s0, w8
+; CHECK-NOFP-GI-NEXT: ret
+;
+; CHECK-FP-GI-LABEL: test_v1f32:
+; CHECK-FP-GI: // %bb.0:
+; CHECK-FP-GI-NEXT: fmov x8, d0
+; CHECK-FP-GI-NEXT: fmov s0, w8
+; CHECK-FP-GI-NEXT: ret
%b = call nnan float @llvm.vector.reduce.fmin.v1f32(<1 x float> %a)
ret float %b
}
@@ -56,203 +88,239 @@ define fp128 @test_v1f128(<1 x fp128> %a) nounwind {
}
define half @test_v4f16(<4 x half> %a) nounwind {
-; CHECK-NOFP-LABEL: test_v4f16:
-; CHECK-NOFP: // %bb.0:
-; CHECK-NOFP-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NOFP-NEXT: mov h1, v0.h[1]
-; CHECK-NOFP-NEXT: fcvt s2, h0
-; CHECK-NOFP-NEXT: fcvt s1, h1
-; CHECK-NOFP-NEXT: fminnm s1, s2, s1
-; CHECK-NOFP-NEXT: mov h2, v0.h[2]
-; CHECK-NOFP-NEXT: mov h0, v0.h[3]
-; CHECK-NOFP-NEXT: fcvt h1, s1
-; CHECK-NOFP-NEXT: fcvt s2, h2
-; CHECK-NOFP-NEXT: fcvt s0, h0
-; CHECK-NOFP-NEXT: fcvt s1, h1
-; CHECK-NOFP-NEXT: fminnm s1, s1, s2
-; CHECK-NOFP-NEXT: fcvt h1, s1
-; CHECK-NOFP-NEXT: fcvt s1, h1
-; CHECK-NOFP-NEXT: fminnm s0, s1, s0
-; CHECK-NOFP-NEXT: fcvt h0, s0
-; CHECK-NOFP-NEXT: ret
+; CHECK-NOFP-SD-LABEL: test_v4f16:
+; CHECK-NOFP-SD: // %bb.0:
+; CHECK-NOFP-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NOFP-SD-NEXT: mov h1, v0.h[1]
+; CHECK-NOFP-SD-NEXT: fcvt s2, h0
+; CHECK-NOFP-SD-NEXT: fcvt s1, h1
+; CHECK-NOFP-SD-NEXT: fminnm s1, s2, s1
+; CHECK-NOFP-SD-NEXT: mov h2, v0.h[2]
+; CHECK-NOFP-SD-NEXT: mov h0, v0.h[3]
+; CHECK-NOFP-SD-NEXT: fcvt h1, s1
+; CHECK-NOFP-SD-NEXT: fcvt s2, h2
+; CHECK-NOFP-SD-NEXT: fcvt s0, h0
+; CHECK-NOFP-SD-NEXT: fcvt s1, h1
+; CHECK-NOFP-SD-NEXT: fminnm s1, s1, s2
+; CHECK-NOFP-SD-NEXT: fcvt h1, s1
+; CHECK-NOFP-SD-NEXT: fcvt s1, h1
+; CHECK-NOFP-SD-NEXT: fminnm s0, s1, s0
+; CHECK-NOFP-SD-NEXT: fcvt h0, s0
+; CHECK-NOFP-SD-NEXT: ret
;
; CHECK-FP-LABEL: test_v4f16:
; CHECK-FP: // %bb.0:
; CHECK-FP-NEXT: fminnmv h0, v0.4h
; CHECK-FP-NEXT: ret
+;
+; CHECK-NOFP-GI-LABEL: test_v4f16:
+; CHECK-NOFP-GI: // %bb.0:
+; CHECK-NOFP-GI-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-NOFP-GI-NEXT: fminnmv s0, v0.4s
+; CHECK-NOFP-GI-NEXT: fcvt h0, s0
+; CHECK-NOFP-GI-NEXT: ret
%b = call nnan half @llvm.vector.reduce.fmin.v4f16(<4 x half> %a)
ret half %b
}
define half @test_v4f16_ninf(<4 x half> %a) nounwind {
-; CHECK-NOFP-LABEL: test_v4f16_ninf:
-; CHECK-NOFP: // %bb.0:
-; CHECK-NOFP-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NOFP-NEXT: mov h1, v0.h[1]
-; CHECK-NOFP-NEXT: fcvt s2, h0
-; CHECK-NOFP-NEXT: fcvt s1, h1
-; CHECK-NOFP-NEXT: fminnm s1, s2, s1
-; CHECK-NOFP-NEXT: mov h2, v0.h[2]
-; CHECK-NOFP-NEXT: mov h0, v0.h[3]
-; CHECK-NOFP-NEXT: fcvt h1, s1
-; CHECK-NOFP-NEXT: fcvt s2, h2
-; CHECK-NOFP-NEXT: fcvt s0, h0
-; CHECK-NOFP-NEXT: fcvt s1, h1
-; CHECK-NOFP-NEXT: fminnm s1, s1, s2
-; CHECK-NOFP-NEXT: fcvt h1, s1
-; CHECK-NOFP-NEXT: fcvt s1, h1
-; CHECK-NOFP-NEXT: fminnm s0, s1, s0
-; CHECK-NOFP-NEXT: fcvt h0, s0
-; CHECK-NOFP-NEXT: ret
+; CHECK-NOFP-SD-LABEL: test_v4f16_ninf:
+; CHECK-NOFP-SD: // %bb.0:
+; CHECK-NOFP-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NOFP-SD-NEXT: mov h1, v0.h[1]
+; CHECK-NOFP-SD-NEXT: fcvt s2, h0
+; CHECK-NOFP-SD-NEXT: fcvt s1, h1
+; CHECK-NOFP-SD-NEXT: fminnm s1, s2, s1
+; CHECK-NOFP-SD-NEXT: mov h2, v0.h[2]
+; CHECK-NOFP-SD-NEXT: mov h0, v0.h[3]
+; CHECK-NOFP-SD-NEXT: fcvt h1, s1
+; CHECK-NOFP-SD-NEXT: fcvt s2, h2
+; CHECK-NOFP-SD-NEXT: fcvt s0, h0
+; CHECK-NOFP-SD-NEXT: fcvt s1, h1
+; CHECK-NOFP-SD-NEXT: fminnm s1, s1, s2
+; CHECK-NOFP-SD-NEXT: fcvt h1, s1
+; CHECK-NOFP-SD-NEXT: fcvt s1, h1
+; CHECK-NOFP-SD-NEXT: fminnm s0, s1, s0
+; CHECK-NOFP-SD-NEXT: fcvt h0, s0
+; CHECK-NOFP-SD-NEXT: ret
;
; CHECK-FP-LABEL: test_v4f16_ninf:
; CHECK-FP: // %bb.0:
; CHECK-FP-NEXT: fminnmv h0, v0.4h
; CHECK-FP-NEXT: ret
+;
+; CHECK-NOFP-GI-LABEL: test_v4f16_ninf:
+; CHECK-NOFP-GI: // %bb.0:
+; CHECK-NOFP-GI-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-NOFP-GI-NEXT: fminnmv s0, v0.4s
+; CHECK-NOFP-GI-NEXT: fcvt h0, s0
+; CHECK-NOFP-GI-NEXT: ret
%b = call nnan ninf half @llvm.vector.reduce.fmin.v4f16(<4 x half> %a)
ret half %b
}
define half @test_v8f16(<8 x half> %a) nounwind {
-; CHECK-NOFP-LABEL: test_v8f16:
-; CHECK-NOFP: // %bb.0:
-; CHECK-NOFP-NEXT: mov h1, v0.h[1]
-; CHECK-NOFP-NEXT: fcvt s2, h0
-; CHECK-NOFP-NEXT: fcvt s1, h1
-; CHECK-NOFP-NEXT: fminnm s1, s2, s1
-; CHECK-NOFP-NEXT: mov h2, v0.h[2]
-; CHECK-NOFP-NEXT: fcvt h1, s1
-; CHECK-NOFP-NEXT: fcvt s2, h2
-; CHECK-NOFP-NEXT: fcvt s1, h1
-; CHECK-NOFP-NEXT: fminnm s1, s1, s2
-; CHECK-NOFP-NEXT: mov h2, v0.h[3]
-; CHECK-NOFP-NEXT: fcvt h1, s1
-; CHECK-NOFP-NEXT: fcvt s2, h2
-; CHECK-NOFP-NEXT: fcvt s1, h1
-; CHECK-NOFP-NEXT: fminnm s1, s1, s2
-; CHECK-NOFP-NEXT: mov h2, v0.h[4]
-; CHECK-NOFP-NEXT: fcvt h1, s1
-; CHECK-NOFP-NEXT: fcvt s2, h2
-; CHECK-NOFP-NEXT: fcvt s1, h1
-; CHECK-NOFP-NEXT: fminnm s1, s1, s2
-; CHECK-NOFP-NEXT: mov h2, v0.h[5]
-; CHECK-NOFP-NEXT: fcvt h1, s1
-; CHECK-NOFP-NEXT: fcvt s2, h2
-; CHECK-NOFP-NEXT: fcvt s1, h1
-; CHECK-NOFP-NEXT: fminnm s1, s1, s2
-; CHECK-NOFP-NEXT: mov h2, v0.h[6]
-; CHECK-NOFP-NEXT: mov h0, v0.h[7]
-; CHECK-NOFP-NEXT: fcvt h1, s1
-; CHECK-NOFP-NEXT: fcvt s2, h2
-; CHECK-NOFP-NEXT: fcvt s0, h0
-; CHECK-NOFP-NEXT: fcvt s1, h1
-; CHECK-NOFP-NEXT: fminnm s1, s1, s2
-; CHECK-NOFP-NEXT: fcvt h1, s1
-; CHECK-NOFP-NEXT: fcvt s1, h1
-; CHECK-NOFP-NEXT: fminnm s0, s1, s0
-; CHECK-NOFP-NEXT: fcvt h0, s0
-; CHECK-NOFP-NEXT: ret
+; CHECK-NOFP-SD-LABEL: test_v8f16:
+; CHECK-NOFP-SD: // %bb.0:
+; CHECK-NOFP-SD-NEXT: mov h1, v0.h[1]
+; CHECK-NOFP-SD-NEXT: fcvt s2, h0
+; CHECK-NOFP-SD-NEXT: fcvt s1, h1
+; CHECK-NOFP-SD-NEXT: fminnm s1, s2, s1
+; CHECK-NOFP-SD-NEXT: mov h2, v0.h[2]
+; CHECK-NOFP-SD-NEXT: fcvt h1, s1
+; CHECK-NOFP-SD-NEXT: fcvt s2, h2
+; CHECK-NOFP-SD-NEXT: fcvt s1, h1
+; CHECK-NOFP-SD-NEXT: fminnm s1, s1, s2
+; CHECK-NOFP-SD-NEXT: mov h2, v0.h[3]
+; CHECK-NOFP-SD-NEXT: fcvt h1, s1
+; CHECK-NOFP-SD-NEXT: fcvt s2, h2
+; CHECK-NOFP-SD-NEXT: fcvt s1, h1
+; CHECK-NOFP-SD-NEXT: fminnm s1, s1, s2
+; CHECK-NOFP-SD-NEXT: mov h2, v0.h[4]
+; CHECK-NOFP-SD-NEXT: fcvt h1, s1
+; CHECK-NOFP-SD-NEXT: fcvt s2, h2
+; CHECK-NOFP-SD-NEXT: fcvt s1, h1
+; CHECK-NOFP-SD-NEXT: fminnm s1, s1, s2
+; CHECK-NOFP-SD-NEXT: mov h2, v0.h[5]
+; CHECK-NOFP-SD-NEXT: fcvt h1, s1
+; CHECK-NOFP-SD-NEXT: fcvt s2, h2
+; CHECK-NOFP-SD-NEXT: fcvt s1, h1
+; CHECK-NOFP-SD-NEXT: fminnm s1, s1, s2
+; CHECK-NOFP-SD-NEXT: mov h2, v0.h[6]
+; CHECK-NOFP-SD-NEXT: mov h0, v0.h[7]
+; CHECK-NOFP-SD-NEXT: fcvt h1, s1
+; CHECK-NOFP-SD-NEXT: fcvt s2, h2
+; CHECK-NOFP-SD-NEXT: fcvt s0, h0
+; CHECK-NOFP-SD-NEXT: fcvt s1, h1
+; CHECK-NOFP-SD-NEXT: fminnm s1, s1, s2
+; CHECK-NOFP-SD-NEXT: fcvt h1, s1
+; CHECK-NOFP-SD-NEXT: fcvt s1, h1
+; CHECK-NOFP-SD-NEXT: fminnm s0, s1, s0
+; CHECK-NOFP-SD-NEXT: fcvt h0, s0
+; CHECK-NOFP-SD-NEXT: ret
;
; CHECK-FP-LABEL: test_v8f16:
; CHECK-FP: // %bb.0:
; CHECK-FP-NEXT: fminnmv h0, v0.8h
; CHECK-FP-NEXT: ret
+;
+; CHECK-NOFP-GI-LABEL: test_v8f16:
+; CHECK-NOFP-GI: // %bb.0:
+; CHECK-NOFP-GI-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-NOFP-GI-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-NOFP-GI-NEXT: fminnm v0.4s, v1.4s, v0.4s
+; CHECK-NOFP-GI-NEXT: fminnmv s0, v0.4s
+; CHECK-NOFP-GI-NEXT: fcvt h0, s0
+; CHECK-NOFP-GI-NEXT: ret
%b = call nnan half @llvm.vector.reduce.fmin.v8f16(<8 x half> %a)
ret half %b
}
define half @test_v16f16(<16 x half> %a) nounwind {
-; CHECK-NOFP-LABEL: test_v16f16:
-; CHECK-NOFP: // %bb.0:
-; CHECK-NOFP-NEXT: mov h2, v1.h[1]
-; CHECK-NOFP-NEXT: mov h3, v0.h[1]
-; CHECK-NOFP-NEXT: fcvt s4, h1
-; CHECK-NOFP-NEXT: fcvt s5, h0
-; CHECK-NOFP-NEXT: fcvt s2, h2
-; CHECK-NOFP-NEXT: fcvt s3, h3
-; CHECK-NOFP-NEXT: fcmp s3, s2
-; CHECK-NOFP-NEXT: fcsel s2, s3, s2, lt
-; CHECK-NOFP-NEXT: fcmp s5, s4
-; CHECK-NOFP-NEXT: fcsel s3, s5, s4, lt
-; CHECK-NOFP-NEXT: mov h4, v1.h[2]
-; CHECK-NOFP-NEXT: mov h5, v0.h[2]
-; CHECK-NOFP-NEXT: fcvt h2, s2
-; CHECK-NOFP-NEXT: fcvt h3, s3
-; CHECK-NOFP-NEXT: fcvt s4, h4
-; CHECK-NOFP-NEXT: fcvt s5, h5
-; CHECK-NOFP-NEXT: fcvt s2, h2
-; CHECK-NOFP-NEXT: fcvt s3, h3
-; CHECK-NOFP-NEXT: fcmp s5, s4
-; CHECK-NOFP-NEXT: fminnm s2, s3, s2
-; CHECK-NOFP-NEXT: fcsel s3, s5, s4, lt
-; CHECK-NOFP-NEXT: mov h4, v1.h[3]
-; CHECK-NOFP-NEXT: mov h5, v0.h[3]
-; CHECK-NOFP-NEXT: fcvt h2, s2
-; CHECK-NOFP-NEXT: fcvt h3, s3
-; CHECK-NOFP-NEXT: fcvt s4, h4
-; CHECK-NOFP-NEXT: fcvt s5, h5
-; CHECK-NOFP-NEXT: fcvt s2, h2
-; CHECK-NOFP-NEXT: fcvt s3, h3
-; CHECK-NOFP-NEXT: fcmp s5, s4
-; CHECK-NOFP-NEXT: fminnm s2, s2, s3
-; CHECK-NOFP-NEXT: fcsel s3, s5, s4, lt
-; CHECK-NOFP-NEXT: mov h4, v1.h[4]
-; CHECK-NOFP-NEXT: mov h5, v0.h[4]
-; CHECK-NOFP-NEXT: fcvt h2, s2
-; CHECK-NOFP-NEXT: fcvt h3, s3
-; CHECK-NOFP-NEXT: fcvt s4, h4
-; CHECK-NOFP-NEXT: fcvt s5, h5
-; CHECK-NOFP-NEXT: fcvt s2, h2
-; CHECK-NOFP-NEXT: fcvt s3, h3
-; CHECK-NOFP-NEXT: fcmp s5, s4
-; CHECK-NOFP-NEXT: fminnm s2, s2, s3
-; CHECK-NOFP-NEXT: fcsel s3, s5, s4, lt
-; CHECK-NOFP-NEXT: mov h4, v1.h[5]
-; CHECK-NOFP-NEXT: mov h5, v0.h[5]
-; CHECK-NOFP-NEXT: fcvt h2, s2
-; CHECK-NOFP-NEXT: fcvt h3, s3
-; CHECK-NOFP-NEXT: fcvt s4, h4
-; CHECK-NOFP-NEXT: fcvt s5, h5
-; CHECK-NOFP-NEXT: fcvt s2, h2
-; CHECK-NOFP-NEXT: fcvt s3, h3
-; CHECK-NOFP-NEXT: fcmp s5, s4
-; CHECK-NOFP-NEXT: fminnm s2, s2, s3
-; CHECK-NOFP-NEXT: fcsel s3, s5, s4, lt
-; CHECK-NOFP-NEXT: mov h4, v1.h[6]
-; CHECK-NOFP-NEXT: mov h5, v0.h[6]
-; CHECK-NOFP-NEXT: mov h1, v1.h[7]
-; CHECK-NOFP-NEXT: mov h0, v0.h[7]
-; CHECK-NOFP-NEXT: fcvt h2, s2
-; CHECK-NOFP-NEXT: fcvt h3, s3
-; CHECK-NOFP-NEXT: fcvt s4, h4
-; CHECK-NOFP-NEXT: fcvt s5, h5
-; CHECK-NOFP-NEXT: fcvt s1, h1
-; CHECK-NOFP-NEXT: fcvt s0, h0
-; CHECK-NOFP-NEXT: fcvt s2, h2
-; CHECK-NOFP-NEXT: fcvt s3, h3
-; CHECK-NOFP-NEXT: fcmp s5, s4
-; CHECK-NOFP-NEXT: fminnm s2, s2, s3
-; CHECK-NOFP-NEXT: fcsel s3, s5, s4, lt
-; CHECK-NOFP-NEXT: fcmp s0, s1
-; CHECK-NOFP-NEXT: fcvt h2, s2
-; CHECK-NOFP-NEXT: fcvt h3, s3
-; CHECK-NOFP-NEXT: fcsel s0, s0, s1, lt
-; CHECK-NOFP-NEXT: fcvt s2, h2
-; CHECK-NOFP-NEXT: fcvt s3, h3
-; CHECK-NOFP-NEXT: fcvt h0, s0
-; CHECK-NOFP-NEXT: fminnm s2, s2, s3
-; CHECK-NOFP-NEXT: fcvt s0, h0
-; CHECK-NOFP-NEXT: fcvt h1, s2
-; CHECK-NOFP-NEXT: fcvt s1, h1
-; CHECK-NOFP-NEXT: fminnm s0, s1, s0
-; CHECK-NOFP-NEXT: fcvt h0, s0
-; CHECK-NOFP-NEXT: ret
+; CHECK-NOFP-SD-LABEL: test_v16f16:
+; CHECK-NOFP-SD: // %bb.0:
+; CHECK-NOFP-SD-NEXT: mov h2, v1.h[1]
+; CHECK-NOFP-SD-NEXT: mov h3, v0.h[1]
+; CHECK-NOFP-SD-NEXT: fcvt s4, h1
+; CHECK-NOFP-SD-NEXT: fcvt s5, h0
+; CHECK-NOFP-SD-NEXT: fcvt s2, h2
+; CHECK-NOFP-SD-NEXT: fcvt s3, h3
+; CHECK-NOFP-SD-NEXT: fcmp s3, s2
+; CHECK-NOFP-SD-NEXT: fcsel s2, s3, s2, lt
+; CHECK-NOFP-SD-NEXT: fcmp s5, s4
+; CHECK-NOFP-SD-NEXT: fcsel s3, s5, s4, lt
+; CHECK-NOFP-SD-NEXT: mov h4, v1.h[2]
+; CHECK-NOFP-SD-NEXT: mov h5, v0.h[2]
+; CHECK-NOFP-SD-NEXT: fcvt h2, s2
+; CHECK-NOFP-SD-NEXT: fcvt h3, s3
+; CHECK-NOFP-SD-NEXT: fcvt s4, h4
+; CHECK-NOFP-SD-NEXT: fcvt s5, h5
+; CHECK-NOFP-SD-NEXT: fcvt s2, h2
+; CHECK-NOFP-SD-NEXT: fcvt s3, h3
+; CHECK-NOFP-SD-NEXT: fcmp s5, s4
+; CHECK-NOFP-SD-NEXT: fminnm s2, s3, s2
+; CHECK-NOFP-SD-NEXT: fcsel s3, s5, s4, lt
+; CHECK-NOFP-SD-NEXT: mov h4, v1.h[3]
+; CHECK-NOFP-SD-NEXT: mov h5, v0.h[3]
+; CHECK-NOFP-SD-NEXT: fcvt h2, s2
+; CHECK-NOFP-SD-NEXT: fcvt h3, s3
+; CHECK-NOFP-SD-NEXT: fcvt s4, h4
+; CHECK-NOFP-SD-NEXT: fcvt s5, h5
+; CHECK-NOFP-SD-NEXT: fcvt s2, h2
+; CHECK-NOFP-SD-NEXT: fcvt s3, h3
+; CHECK-NOFP-SD-NEXT: fcmp s5, s4
+; CHECK-NOFP-SD-NEXT: fminnm s2, s2, s3
+; CHECK-NOFP-SD-NEXT: fcsel s3, s5, s4, lt
+; CHECK-NOFP-SD-NEXT: mov h4, v1.h[4]
+; CHECK-NOFP-SD-NEXT: mov h5, v0.h[4]
+; CHECK-NOFP-SD-NEXT: fcvt h2, s2
+; CHECK-NOFP-SD-NEXT: fcvt h3, s3
+; CHECK-NOFP-SD-NEXT: fcvt s4, h4
+; CHECK-NOFP-SD-NEXT: fcvt s5, h5
+; CHECK-NOFP-SD-NEXT: fcvt s2, h2
+; CHECK-NOFP-SD-NEXT: fcvt s3, h3
+; CHECK-NOFP-SD-NEXT: fcmp s5, s4
+; CHECK-NOFP-SD-NEXT: fminnm s2, s2, s3
+; CHECK-NOFP-SD-NEXT: fcsel s3, s5, s4, lt
+; CHECK-NOFP-SD-NEXT: mov h4, v1.h[5]
+; CHECK-NOFP-SD-NEXT: mov h5, v0.h[5]
+; CHECK-NOFP-SD-NEXT: fcvt h2, s2
+; CHECK-NOFP-SD-NEXT: fcvt h3, s3
+; CHECK-NOFP-SD-NEXT: fcvt s4, h4
+; CHECK-NOFP-SD-NEXT: fcvt s5, h5
+; CHECK-NOFP-SD-NEXT: fcvt s2, h2
+; CHECK-NOFP-SD-NEXT: fcvt s3, h3
+; CHECK-NOFP-SD-NEXT: fcmp s5, s4
+; CHECK-NOFP-SD-NEXT: fminnm s2, s2, s3
+; CHECK-NOFP-SD-NEXT: fcsel s3, s5, s4, lt
+; CHECK-NOFP-SD-NEXT: mov h4, v1.h[6]
+; CHECK-NOFP-SD-NEXT: mov h5, v0.h[6]
+; CHECK-NOFP-SD-NEXT: mov h1, v1.h[7]
+; CHECK-NOFP-SD-NEXT: mov h0, v0.h[7]
+; CHECK-NOFP-SD-NEXT: fcvt h2, s2
+; CHECK-NOFP-SD-NEXT: fcvt h3, s3
+; CHECK-NOFP-SD-NEXT: fcvt s4, h4
+; CHECK-NOFP-SD-NEXT: fcvt s5, h5
+; CHECK-NOFP-SD-NEXT: fcvt s1, h1
+; CHECK-NOFP-SD-NEXT: fcvt s0, h0
+; CHECK-NOFP-SD-NEXT: fcvt s2, h2
+; CHECK-NOFP-SD-NEXT: fcvt s3, h3
+; CHECK-NOFP-SD-NEXT: fcmp s5, s4
+; CHECK-NOFP-SD-NEXT: fminnm s2, s2, s3
+; CHECK-NOFP-SD-NEXT: fcsel s3, s5, s4, lt
+; CHECK-NOFP-SD-NEXT: fcmp s0, s1
+; CHECK-NOFP-SD-NEXT: fcvt h2, s2
+; CHECK-NOFP-SD-NEXT: fcvt h3, s3
+; CHECK-NOFP-SD-NEXT: fcsel s0, s0, s1, lt
+; CHECK-NOFP-SD-NEXT: fcvt s2, h2
+; CHECK-NOFP-SD-NEXT: fcvt s3, h3
+; CHECK-NOFP-SD-NEXT: fcvt h0, s0
+; CHECK-NOFP-SD-NEXT: fminnm s2, s2, s3
+; CHECK-NOFP-SD-NEXT: fcvt s0, h0
+; CHECK-NOFP-SD-NEXT: fcvt h1, s2
+; CHECK-NOFP-SD-NEXT: fcvt s1, h1
+; CHECK-NOFP-SD-NEXT: fminnm s0, s1, s0
+; CHECK-NOFP-SD-NEXT: fcvt h0, s0
+; CHECK-NOFP-SD-NEXT: ret
;
; CHECK-FP-LABEL: test_v16f16:
; CHECK-FP: // %bb.0:
; CHECK-FP-NEXT: fminnm v0.8h, v0.8h, v1.8h
; CHECK-FP-NEXT: fminnmv h0, v0.8h
; CHECK-FP-NEXT: ret
+;
+; CHECK-NOFP-GI-LABEL: test_v16f16:
+; CHECK-NOFP-GI: // %bb.0:
+; CHECK-NOFP-GI-NEXT: fcvtl v2.4s, v0.4h
+; CHECK-NOFP-GI-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-NOFP-GI-NEXT: fcvtl v3.4s, v1.4h
+; CHECK-NOFP-GI-NEXT: fcvtl2 v1.4s, v1.8h
+; CHECK-NOFP-GI-NEXT: fminnm v0.4s, v2.4s, v0.4s
+; CHECK-NOFP-GI-NEXT: fminnm v1.4s, v3.4s, v1.4s
+; CHECK-NOFP-GI-NEXT: fminnm v0.4s, v0.4s, v1.4s
+; CHECK-NOFP-GI-NEXT: fminnmv s0, v0.4s
+; CHECK-NOFP-GI-NEXT: fcvt h0, s0
+; CHECK-NOFP-GI-NEXT: ret
%b = call nnan half @llvm.vector.reduce.fmin.v16f16(<16 x half> %a)
ret half %b
}
@@ -286,13 +354,37 @@ define float @test_v8f32(<8 x float> %a) nounwind {
}
define float @test_v16f32(<16 x float> %a) nounwind {
-; CHECK-LABEL: test_v16f32:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fminnm v1.4s, v1.4s, v3.4s
-; CHECK-NEXT: fminnm v0.4s, v0.4s, v2.4s
-; CHECK-NEXT: fminnm v0.4s, v0.4s, v1.4s
-; CHECK-NEXT: fminnmv s0, v0.4s
-; CHECK-NEXT: ret
+; CHECK-NOFP-SD-LABEL: test_v16f32:
+; CHECK-NOFP-SD: // %bb.0:
+; CHECK-NOFP-SD-NEXT: fminnm v1.4s, v1.4s, v3.4s
+; CHECK-NOFP-SD-NEXT: fminnm v0.4s, v0.4s, v2.4s
+; CHECK-NOFP-SD-NEXT: fminnm v0.4s, v0.4s, v1.4s
+; CHECK-NOFP-SD-NEXT: fminnmv s0, v0.4s
+; CHECK-NOFP-SD-NEXT: ret
+;
+; CHECK-FP-SD-LABEL: test_v16f32:
+; CHECK-FP-SD: // %bb.0:
+; CHECK-FP-SD-NEXT: fminnm v1.4s, v1.4s, v3.4s
+; CHECK-FP-SD-NEXT: fminnm v0.4s, v0.4s, v2.4s
+; CHECK-FP-SD-NEXT: fminnm v0.4s, v0.4s, v1.4s
+; CHECK-FP-SD-NEXT: fminnmv s0, v0.4s
+; CHECK-FP-SD-NEXT: ret
+;
+; CHECK-NOFP-GI-LABEL: test_v16f32:
+; CHECK-NOFP-GI: // %bb.0:
+; CHECK-NOFP-GI-NEXT: fminnm v0.4s, v0.4s, v1.4s
+; CHECK-NOFP-GI-NEXT: fminnm v1.4s, v2.4s, v3.4s
+; CHECK-NOFP-GI-NEXT: fminnm v0.4s, v0.4s, v1.4s
+; CHECK-NOFP-GI-NEXT: fminnmv s0, v0.4s
+; CHECK-NOFP-GI-NEXT: ret
+;
+; CHECK-FP-GI-LABEL: test_v16f32:
+; CHECK-FP-GI: // %bb.0:
+; CHECK-FP-GI-NEXT: fminnm v0.4s, v0.4s, v1.4s
+; CHECK-FP-GI-NEXT: fminnm v1.4s, v2.4s, v3.4s
+; CHECK-FP-GI-NEXT: fminnm v0.4s, v0.4s, v1.4s
+; CHECK-FP-GI-NEXT: fminnmv s0, v0.4s
+; CHECK-FP-GI-NEXT: ret
%b = call nnan float @llvm.vector.reduce.fmin.v16f32(<16 x float> %a)
ret float %b
}
More information about the llvm-commits
mailing list