[PATCH] D157089: [AMDGPU] Fix dealing with register interval endpoints in SIInsertWaitcnts.

[Ivan Kosarev via Phabricator via llvm-commits]

kosarev updated this revision to Diff 548942.
kosarev added a comment.

Rebased on the current top of tree. Remove dependency on D157088 <https://reviews.llvm.org/D157088>.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D157089/new/

https://reviews.llvm.org/D157089

Files:
  llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp


Index: llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+++ llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
@@ -506,7 +506,7 @@
   unsigned Reg = TRI->getEncodingValue(AMDGPU::getMCReg(Op.getReg(), *ST));
 
   if (TRI->isVectorRegister(*MRI, Op.getReg())) {
-    assert(Reg >= Encoding.VGPR0 && Reg <= Encoding.VGPRL);
+    assert(Reg >= Encoding.VGPR0 && Reg < Encoding.VGPRL);
     Result.first = Reg - Encoding.VGPR0;
     if (TRI->isAGPR(*MRI, Op.getReg()))
       Result.first += AGPR_OFFSET;
@@ -1830,9 +1830,9 @@
 
   RegisterEncoding Encoding = {};
   Encoding.VGPR0 = TRI->getEncodingValue(AMDGPU::VGPR0);
-  Encoding.VGPRL = Encoding.VGPR0 + NumVGPRsMax - 1;
+  Encoding.VGPRL = Encoding.VGPR0 + NumVGPRsMax;
   Encoding.SGPR0 = TRI->getEncodingValue(AMDGPU::SGPR0);
-  Encoding.SGPRL = Encoding.SGPR0 + NumSGPRsMax - 1;
+  Encoding.SGPRL = Encoding.SGPR0 + NumSGPRsMax;
 
   TrackedWaitcntSet.clear();
   BlockInfos.clear();


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