[PATCH] D156909: [RISCV] Use NoReg in place of IMPLICIT_DEF for undefined passthru operands

[Philip Reames via Phabricator via llvm-commits]

reames added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll:440
+; RV32-NEXT:    vsetivli zero, 1, e8, mf8, ta, ma
+; RV32-NEXT:    vmv.v.i v0, 5
 ; RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
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luke wrote:
> Possible regression here. Are the NoRegs coming into the InsertVSETVLI pass? 
This turns out to be a known issue showing up in a slightly surprising way.

The cause is that InsertVSETVLI contains a peephole for VL=1 splats with tail undefined which is only applied in the forward direction - due to staleness issues.

The scheduling changes causing the two vmv.v.i instructions to be reordered.  So previously the VL=4 e32 comes before the VL=1 e8.  Afterward, the inverse order reaches InsertVSETVLI and the forward rule doesn't trigger.

The fix here would be to always apply peepholes in both directions, but that requires careful reasoning about working with stale MI.  I'll think about that separately, but do not consider this a blocker for this patch.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156909/new/

https://reviews.llvm.org/D156909