[PATCH] D156909: [RISCV] Use NoReg in place of IMPLICIT_DEF for undefined passthru operands

[Luke Lau via Phabricator via llvm-commits]

luke added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll:440
+; RV32-NEXT:    vsetivli zero, 1, e8, mf8, ta, ma
+; RV32-NEXT:    vmv.v.i v0, 5
 ; RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
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Possible regression here. Are the NoRegs coming into the InsertVSETVLI pass? 


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156909/new/

https://reviews.llvm.org/D156909