[PATCH] D157077: [RISCV] Teach VSETVLIInserter to not demand tail policy when there is no tail element

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:820
+      InstrInfo.hasAVLReg() && InstrInfo.getAVLReg() == RISCV::X0 &&
+      VLMul < RISCVII::LMUL_RESERVED)
+    TailAgnostic = true;
----------------
`!decodeVLMUL(VLMul).second`


================
Comment at: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:979
+      // Fractional LMULs always require tail policy.
+      if (VLMul < RISCVII::LMUL_RESERVED) {
+        const MachineOperand &VLOp = MI.getOperand(getVLOpNum(MI));
----------------
`!decodeVLMUL(VLMul).second`


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D157077/new/

https://reviews.llvm.org/D157077