[PATCH] D157077: [RISCV] Teach VSETVLIInserter to not demand tail policy when there is no tail element
Jianjian Guan via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 8 00:32:46 PDT 2023
jacquesguan marked an inline comment as done.
jacquesguan added inline comments.
================
Comment at: llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll:585
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a0, zero, e64, m1, tu, mu
+; CHECK-NEXT: vadd.vv v8, v8, v8, v0.t
----------------
craig.topper wrote:
> Wouldn't we want ta instead of tu since there is no tail?
Done.
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rG LLVM Github Monorepo
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https://reviews.llvm.org/D157077/new/
https://reviews.llvm.org/D157077
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