[PATCH] D157279: [CodeGen] Disable FP LD1RX instructions generation for Neoverse-V1

[Igor Kirillov via Phabricator via llvm-commits]

igor.kirillov updated this revision to Diff 548141.
igor.kirillov marked an inline comment as done.
igor.kirillov added a comment.

- Add RUN line to sve-ld1r.ll test with -mcpu=neoverse-v1
- Update feature description
- Add missing Predicate


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D157279/new/

https://reviews.llvm.org/D157279

Files:
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/CodeGen/AArch64/sve-ld1r.ll

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