[PATCH] D157250: [RISCV] Enable alias analysis by default

[Kito Cheng via Phabricator via llvm-commits]

kito-cheng added a comment.

eral, but I would like defer the final decision to @asb and @craig.topper



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Comment at: llvm/test/CodeGen/RISCV/vararg.ll:498-499
 ; ILP32-ILP32F-FPELIM-NEXT:    sw a2, 24(sp)
+; ILP32-ILP32F-FPELIM-NEXT:    addi a0, sp, 20
+; ILP32-ILP32F-FPELIM-NEXT:    sw a0, 12(sp)
 ; ILP32-ILP32F-FPELIM-NEXT:    addi a0, sp, 27
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Yunzezhu wrote:
> kito-cheng wrote:
> > Ooops, why we got an extra store here after enable AA ?
> > Ooops, why we got an extra store here after enable AA ?
> 
> When AA is not enabled, a store node is legalized from vastart, this node is not parallel with other store nodes and is not directly chained to token factor, so in later combine this node becomes dead node and get removed.
> When AA is enabled, this store node is made parallel with other store nodes and chained to same token factor, so it is not seen as dead node and remains after combining.
Thank you for explanation :) I am OK with this little code gen degradation since enable AA sounds reasonable in general, but I would like defer the final decision to @asb and @craig.topper 


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  https://reviews.llvm.org/D157250/new/

https://reviews.llvm.org/D157250