[PATCH] D157373: [RISCV] add a compress optimization for stack inst.

[lcvon via Phabricator via llvm-commits]

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For callee save/restored operation, it mostly uses the
following inst patterns:

  sw rs2, offset(x2)
  sd rs2, offset(x2)
  fsw rs2, offset(x2)
  fsd rs2, offset(x2)
  lw rd, offset(x2)
  ld rd, offset(x2)
  flw rd, offset(x2)
  fld rd, offset(x2)

and offset decides whether the instructions can be compressed.
now offset 2032 will be set by default if stacksize is larger
than 2^12-1 to save and restore callee saved register, so it
will prevent all the callee saved stack insts be compressed.

Allocate proper offset for stack insts is useful to decrease
the codesize and improve performance and add an option
riscv-compress-stack-inst to control whether to do this
optimization.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D157373

Files:
  llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
  llvm/test/CodeGen/RISCV/compress-stack.mir

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