[PATCH] D152714: [AArch64][Optimization]Emit FCCMP for AND of two float compares

[Priyanshi Agarwal via Phabricator via llvm-commits]

ipriyanshi1708 added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:16418-16419
+      return DAG.getNode(AArch64ISD::CSINC, DL, VT,
+                         DAG.getRegister(ZeroReg, VT),
+                         DAG.getRegister(ZeroReg, VT),
+                         DAG.getConstant(InvertedCC, DL, MVT::i32), Cmp);
----------------
dmgreen wrote:
> ipriyanshi1708 wrote:
> > dmgreen wrote:
> > > I think these may be better as DAG.getConstant(0, DL, VT), as opposed to AArch64::WZR / AArch64::XZR. They should get converted to the same thing eventually, but having zero constant's will be easier for the rest of DAG to reason about.
> > Yup! I tried that too but it was generating this instruction "cset	w0, ne" instead of this one "cset    w0, vs".
> Is that with something like this?
> ```
> return DAG.getNode(AArch64ISD::CSINC, DL, VT,                      
>                    DAG.getConstant(0, DL, VT),
>                    DAG.getConstant(0, DL, VT),
>                    DAG.getConstant(InvertedCC, DL, MVT::i32), Cmp);
> ```
Ohh! yes it is correct. Earlier I have replaced `DAG.getConstant(InvertedCC, DL, MVT::i32), Cmp);` with `DAG.getConstant(0, DL, VT)` that's why it was not working.


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  https://reviews.llvm.org/D152714/new/

https://reviews.llvm.org/D152714