[PATCH] D152714: [AArch64][Optimization]Emit FCCMP for AND of two float compares

[Dave Green via Phabricator via llvm-commits]

dmgreen added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:16418-16419
+      return DAG.getNode(AArch64ISD::CSINC, DL, VT,
+                         DAG.getRegister(ZeroReg, VT),
+                         DAG.getRegister(ZeroReg, VT),
+                         DAG.getConstant(InvertedCC, DL, MVT::i32), Cmp);
----------------
ipriyanshi1708 wrote:
> dmgreen wrote:
> > I think these may be better as DAG.getConstant(0, DL, VT), as opposed to AArch64::WZR / AArch64::XZR. They should get converted to the same thing eventually, but having zero constant's will be easier for the rest of DAG to reason about.
> Yup! I tried that too but it was generating this instruction "cset	w0, ne" instead of this one "cset    w0, vs".
Is that with something like this?
```
return DAG.getNode(AArch64ISD::CSINC, DL, VT,                      
                   DAG.getConstant(0, DL, VT),
                   DAG.getConstant(0, DL, VT),
                   DAG.getConstant(InvertedCC, DL, MVT::i32), Cmp);
```


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D152714/new/

https://reviews.llvm.org/D152714