[PATCH] D157231: [SPARC][IAS] Add definitions for v9 State Registers

[Sergei Barannikov via Phabricator via llvm-commits]

barannikov88 added inline comments.


================
Comment at: llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp:1320
 
     // %fprs is an alias of %asr6.
     if (name.equals("fprs")) {
----------------
I guess this comment can be removed.


================
Comment at: llvm/lib/Target/Sparc/SparcInstrAliases.td:527
 def : InstAlias<"mov %tbr, $rd", (RDTBR IntRegs:$rd), 0>;
-def : InstAlias<"mov %pc, $rd", (RDPC IntRegs:$rd), 0>;
+def : InstAlias<"mov %pc, $rd", (RDASR IntRegs:$rd, PC), 0>;
 
----------------
Isn't this covered by the first InstAlias in the group?



================
Comment at: llvm/lib/Target/Sparc/SparcRegisterInfo.td:135
+def GL         : SparcCtrlReg<16, "GL">;
+def VER        : SparcCtrlReg<31, "VER">;
 
----------------
It looks like these registers are actually aliases to %asrXX (or vice versa). They should use the corresponding functionality instead of being redefined.
See RegAltNameIndex in Target.td and how other targets use it.



================
Comment at: llvm/lib/Target/Sparc/SparcRegisterInfo.td:375
+                              (add Y, CCR, ASI, TICK, PC, FPRS,
+                               (sequence "ASR%u", 1, 31))>;
 
----------------
See the comment above about RegAltNameIndex.



================
Comment at: llvm/test/MC/Sparc/sparcv9-instructions.s:425
         ! V9: rd %pc, %o7               ! encoding: [0x9f,0x41,0x40,0x00]
         rd %pc, %o7
+        ! V9: rd %asi, %g1              ! encoding: [0x83,0x40,0xc0,0x00]
----------------
IIUC all of these should complain about missing feature on V8. This can probably be done by adding some checks to validateTargetOperandClass or checkTargetMatchPredicate.



Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D157231/new/

https://reviews.llvm.org/D157231