[PATCH] D157230: [SPARC][IAS] Add SETX pseudoinstruction

Sergei Barannikov via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Sun Aug 6 12:41:02 PDT 2023


barannikov88 added inline comments.


================
Comment at: llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp:659
+  if (!is64Bit())
+    return Error(IDLoc, "setx is only available in 64-bit mode");
+
----------------
Looks like dead code (MatchInstructionImpl should return Match_MissingFeature). Can you add a test for this as in D144936?



================
Comment at: llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp:662
+  // the imm operand can be either an expression or an immediate.
+  bool IsImm = Inst.getOperand(1).isImm();
+  int64_t ImmValue = IsImm ? MCValOp.getImm() : 0;
----------------



================
Comment at: llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp:667
+  if (isUInt<32>(ImmValue))
+    return expandSET(Inst, IDLoc, Instructions);
+
----------------
This will be executed if the operand is an expression. This is probably not desired. Please add a test.



================
Comment at: llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp:670
+  // Small negative immediates can be expressed directly as a single `or`.
+  bool IsSmallNegative = ImmValue >= -4096 && ImmValue <= 0;
+  if (IsImm && IsSmallNegative) {
----------------



================
Comment at: llvm/lib/Target/Sparc/SparcInstrAliases.td:449-451
+  (ins i64imm:$val, I64Regs:$tmp),
+  "setx $val, $tmp, $rd">,
+  Requires<[Is64Bit]>;
----------------
Wrapped lines should be aligned after '<'.



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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D157230/new/

https://reviews.llvm.org/D157230



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