[llvm] ffc5ed9 - [AArch64][GISel] Expand handling for G_FABS to more vector types.
David Green via llvm-commits
llvm-commits at lists.llvm.org
Sun Aug 6 06:58:30 PDT 2023
Author: David Green
Date: 2023-08-06T14:58:25+01:00
New Revision: ffc5ed976a47b28a7b59673614e6f0bac770c4a9
URL: https://github.com/llvm/llvm-project/commit/ffc5ed976a47b28a7b59673614e6f0bac770c4a9
DIFF: https://github.com/llvm/llvm-project/commit/ffc5ed976a47b28a7b59673614e6f0bac770c4a9.diff
LOG: [AArch64][GISel] Expand handling for G_FABS to more vector types.
This now reuses the existing lowering for G_FMIN/MAX for G_FABS too, which can
handle more type successfully. We can hopefully reuse the same pattern action
definition for other fp operations too.
Added:
Modified:
llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
llvm/test/CodeGen/AArch64/arm64-vfloatintrinsics.ll
llvm/test/CodeGen/AArch64/fabs.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index ecdab74ce0593e..a9569caeb872cb 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -243,7 +243,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
getActionDefinitionsBuilder(G_FREM).libcallFor({s32, s64});
- getActionDefinitionsBuilder({G_FCEIL, G_FABS, G_FSQRT, G_FFLOOR, G_FRINT,
+ getActionDefinitionsBuilder({G_FCEIL, G_FSQRT, G_FFLOOR, G_FRINT,
G_FMA, G_INTRINSIC_TRUNC, G_INTRINSIC_ROUND,
G_FNEARBYINT, G_INTRINSIC_LRINT})
// If we don't have full FP16 support, then scalarize the elements of
@@ -919,7 +919,8 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
// TODO: Vector types.
getActionDefinitionsBuilder({G_SADDSAT, G_SSUBSAT}).lowerIf(isScalar(0));
- getActionDefinitionsBuilder({G_FMAXNUM, G_FMINNUM, G_FMAXIMUM, G_FMINIMUM})
+ getActionDefinitionsBuilder(
+ {G_FABS, G_FMAXNUM, G_FMINNUM, G_FMAXIMUM, G_FMINIMUM})
.legalFor({MinFPScalar, s32, s64, v2s32, v4s32, v2s64})
.legalIf([=](const LegalityQuery &Query) {
const auto &Ty = Query.Types[0];
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
index 65ab99627da29a..55dcbc255e69e6 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
@@ -513,7 +513,6 @@
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: G_FABS (opcode {{[0-9]+}}): 1 type index, 0 imm indices
-# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: G_FCOPYSIGN (opcode {{[0-9]+}}): 2 type indices
@@ -530,6 +529,7 @@
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: G_FMAXNUM (opcode {{[0-9]+}}): 1 type index
+# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: G_FMINNUM_IEEE (opcode {{[0-9]+}}): 1 type index
diff --git a/llvm/test/CodeGen/AArch64/arm64-vfloatintrinsics.ll b/llvm/test/CodeGen/AArch64/arm64-vfloatintrinsics.ll
index e5ce26ec9fe3af..fd4005532e9243 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vfloatintrinsics.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vfloatintrinsics.ll
@@ -144,7 +144,7 @@ define %v4f16 @test_v4f16.fabs(%v4f16 %a) {
; CHECK-FP16-NEXT: ret
; GISEL-LABEL: test_v4f16.fabs:
- ; GISEL-NOFP16-COUNT-4: fabs s{{[0-9]+}}, s{{[0-9]+}}
+ ; GISEL-NOFP16: fabs.4s
; GISEL-FP16-NOT: fcvt
; GISEL-FP16: fabs.4h
; GISEL-FP16-NEXT: ret
@@ -416,7 +416,7 @@ define %v8f16 @test_v8f16.fabs(%v8f16 %a) {
; CHECK-FP16-NEXT: ret
; GISEL-LABEL: test_v8f16.fabs:
- ; GISEL-NOFP16-COUNT-8: fabs s{{[0-9]+}}, s{{[0-9]+}}
+ ; GISEL-NOFP16-COUNT-2: fabs.4s
; GISEL-FP16-NOT: fcvt
; GISEL-FP16: fabs.8h
; GISEL-FP16-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/fabs.ll b/llvm/test/CodeGen/AArch64/fabs.ll
index 054b9bc6870e4b..37c6ec98ce641e 100644
--- a/llvm/test/CodeGen/AArch64/fabs.ll
+++ b/llvm/test/CodeGen/AArch64/fabs.ll
@@ -1,14 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -mtriple=aarch64-none-eabi -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD,CHECK-SD-NOFP16
; RUN: llc -mtriple=aarch64-none-eabi -mattr=+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD,CHECK-SD-FP16
-; RUN: llc -mtriple=aarch64-none-eabi -global-isel -global-isel-abort=2 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI,CHECK-GI-NOFP16
-; RUN: llc -mtriple=aarch64-none-eabi -mattr=+fullfp16 -global-isel -global-isel-abort=2 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI,CHECK-GI-FP16
-
-; CHECK-GI: warning: Instruction selection used fallback path for fabs_v3f64
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fabs_v4f64
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fabs_v3f32
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fabs_v8f32
-; CHECK-GI-FP16-NEXT: warning: Instruction selection used fallback path for fabs_v16f16
+; RUN: llc -mtriple=aarch64-none-eabi -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI,CHECK-GI-NOFP16
+; RUN: llc -mtriple=aarch64-none-eabi -mattr=+fullfp16 -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI,CHECK-GI-FP16
define double @fabs_f64(double %a) {
; CHECK-LABEL: fabs_f64:
@@ -70,19 +64,30 @@ entry:
}
define <3 x double> @fabs_v3f64(<3 x double> %a) {
-; CHECK-LABEL: fabs_v3f64:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-NEXT: // kill: def $d2 killed $d2 def $q2
-; CHECK-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-NEXT: fabs v2.2d, v2.2d
-; CHECK-NEXT: // kill: def $d2 killed $d2 killed $q2
-; CHECK-NEXT: fabs v0.2d, v0.2d
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-NEXT: // kill: def $d1 killed $d1 killed $q1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: fabs_v3f64:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-SD-NEXT: // kill: def $d2 killed $d2 def $q2
+; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-SD-NEXT: fabs v2.2d, v2.2d
+; CHECK-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
+; CHECK-SD-NEXT: fabs v0.2d, v0.2d
+; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: fabs_v3f64:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-GI-NEXT: fabs d2, d2
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: fabs v0.2d, v0.2d
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: ret
entry:
%c = call <3 x double> @llvm.fabs.v3f64(<3 x double> %a)
ret <3 x double> %c
@@ -110,10 +115,25 @@ entry:
}
define <3 x float> @fabs_v3f32(<3 x float> %a) {
-; CHECK-LABEL: fabs_v3f32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fabs v0.4s, v0.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: fabs_v3f32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: fabs v0.4s, v0.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: fabs_v3f32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: mov s1, v0.s[1]
+; CHECK-GI-NEXT: mov s2, v0.s[2]
+; CHECK-GI-NEXT: mov v0.s[1], v1.s[0]
+; CHECK-GI-NEXT: mov v0.s[2], v2.s[0]
+; CHECK-GI-NEXT: mov v0.s[3], v0.s[0]
+; CHECK-GI-NEXT: fabs v0.4s, v0.4s
+; CHECK-GI-NEXT: mov s1, v0.s[1]
+; CHECK-GI-NEXT: mov s2, v0.s[2]
+; CHECK-GI-NEXT: mov v0.s[1], v1.s[0]
+; CHECK-GI-NEXT: mov v0.s[2], v2.s[0]
+; CHECK-GI-NEXT: mov v0.s[3], v0.s[0]
+; CHECK-GI-NEXT: ret
entry:
%c = call <3 x float> @llvm.fabs.v3f32(<3 x float> %a)
ret <3 x float> %c
@@ -172,26 +192,9 @@ define <4 x half> @fabs_v4f16(<4 x half> %a) {
;
; CHECK-GI-NOFP16-LABEL: fabs_v4f16:
; CHECK-GI-NOFP16: // %bb.0: // %entry
-; CHECK-GI-NOFP16-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NOFP16-NEXT: mov h1, v0.h[1]
-; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[2]
-; CHECK-GI-NOFP16-NEXT: fcvt s3, h0
-; CHECK-GI-NOFP16-NEXT: mov h0, v0.h[3]
-; CHECK-GI-NOFP16-NEXT: fcvt s1, h1
-; CHECK-GI-NOFP16-NEXT: fcvt s2, h2
-; CHECK-GI-NOFP16-NEXT: fabs s3, s3
-; CHECK-GI-NOFP16-NEXT: fcvt s4, h0
-; CHECK-GI-NOFP16-NEXT: fabs s1, s1
-; CHECK-GI-NOFP16-NEXT: fabs s2, s2
-; CHECK-GI-NOFP16-NEXT: fcvt h0, s3
-; CHECK-GI-NOFP16-NEXT: fabs s3, s4
-; CHECK-GI-NOFP16-NEXT: fcvt h1, s1
-; CHECK-GI-NOFP16-NEXT: fcvt h2, s2
-; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v1.h[0]
-; CHECK-GI-NOFP16-NEXT: fcvt h1, s3
-; CHECK-GI-NOFP16-NEXT: mov v0.h[2], v2.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.h[3], v1.h[0]
-; CHECK-GI-NOFP16-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NOFP16-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-GI-NOFP16-NEXT: fabs v0.4s, v0.4s
+; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v0.4s
; CHECK-GI-NOFP16-NEXT: ret
;
; CHECK-GI-FP16-LABEL: fabs_v4f16:
@@ -254,45 +257,12 @@ define <8 x half> @fabs_v8f16(<8 x half> %a) {
;
; CHECK-GI-NOFP16-LABEL: fabs_v8f16:
; CHECK-GI-NOFP16: // %bb.0: // %entry
-; CHECK-GI-NOFP16-NEXT: mov h1, v0.h[1]
-; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[2]
-; CHECK-GI-NOFP16-NEXT: fcvt s3, h0
-; CHECK-GI-NOFP16-NEXT: mov h4, v0.h[3]
-; CHECK-GI-NOFP16-NEXT: mov h6, v0.h[4]
-; CHECK-GI-NOFP16-NEXT: fcvt s1, h1
-; CHECK-GI-NOFP16-NEXT: fcvt s2, h2
-; CHECK-GI-NOFP16-NEXT: fabs s3, s3
-; CHECK-GI-NOFP16-NEXT: fcvt s4, h4
-; CHECK-GI-NOFP16-NEXT: fcvt s6, h6
-; CHECK-GI-NOFP16-NEXT: fabs s5, s1
-; CHECK-GI-NOFP16-NEXT: fabs s2, s2
-; CHECK-GI-NOFP16-NEXT: fcvt h1, s3
-; CHECK-GI-NOFP16-NEXT: fabs s4, s4
-; CHECK-GI-NOFP16-NEXT: fabs s6, s6
-; CHECK-GI-NOFP16-NEXT: fcvt h3, s5
-; CHECK-GI-NOFP16-NEXT: mov h5, v0.h[5]
-; CHECK-GI-NOFP16-NEXT: fcvt h2, s2
-; CHECK-GI-NOFP16-NEXT: fcvt h4, s4
-; CHECK-GI-NOFP16-NEXT: mov v1.h[1], v3.h[0]
-; CHECK-GI-NOFP16-NEXT: mov h3, v0.h[6]
-; CHECK-GI-NOFP16-NEXT: fcvt s5, h5
-; CHECK-GI-NOFP16-NEXT: mov h0, v0.h[7]
-; CHECK-GI-NOFP16-NEXT: mov v1.h[2], v2.h[0]
-; CHECK-GI-NOFP16-NEXT: fcvt s3, h3
-; CHECK-GI-NOFP16-NEXT: fabs s2, s5
-; CHECK-GI-NOFP16-NEXT: fcvt h5, s6
-; CHECK-GI-NOFP16-NEXT: fcvt s0, h0
-; CHECK-GI-NOFP16-NEXT: mov v1.h[3], v4.h[0]
-; CHECK-GI-NOFP16-NEXT: fabs s3, s3
-; CHECK-GI-NOFP16-NEXT: fcvt h2, s2
-; CHECK-GI-NOFP16-NEXT: fabs s0, s0
-; CHECK-GI-NOFP16-NEXT: mov v1.h[4], v5.h[0]
-; CHECK-GI-NOFP16-NEXT: fcvt h3, s3
-; CHECK-GI-NOFP16-NEXT: fcvt h0, s0
-; CHECK-GI-NOFP16-NEXT: mov v1.h[5], v2.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v1.h[6], v3.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v1.h[7], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.16b, v1.16b
+; CHECK-GI-NOFP16-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-GI-NOFP16-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-GI-NOFP16-NEXT: fabs v1.4s, v1.4s
+; CHECK-GI-NOFP16-NEXT: fabs v2.4s, v0.4s
+; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v1.4s
+; CHECK-GI-NOFP16-NEXT: fcvtn2 v0.8h, v2.4s
; CHECK-GI-NOFP16-NEXT: ret
;
; CHECK-GI-FP16-LABEL: fabs_v8f16:
@@ -395,84 +365,18 @@ define <16 x half> @fabs_v16f16(<16 x half> %a) {
;
; CHECK-GI-NOFP16-LABEL: fabs_v16f16:
; CHECK-GI-NOFP16: // %bb.0: // %entry
-; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[1]
-; CHECK-GI-NOFP16-NEXT: mov h3, v1.h[1]
-; CHECK-GI-NOFP16-NEXT: fcvt s4, h0
-; CHECK-GI-NOFP16-NEXT: fcvt s5, h1
-; CHECK-GI-NOFP16-NEXT: mov h6, v0.h[2]
-; CHECK-GI-NOFP16-NEXT: mov h7, v1.h[2]
-; CHECK-GI-NOFP16-NEXT: mov h18, v0.h[3]
-; CHECK-GI-NOFP16-NEXT: mov h19, v1.h[3]
-; CHECK-GI-NOFP16-NEXT: fcvt s2, h2
-; CHECK-GI-NOFP16-NEXT: fcvt s3, h3
-; CHECK-GI-NOFP16-NEXT: fabs s4, s4
-; CHECK-GI-NOFP16-NEXT: fabs s5, s5
-; CHECK-GI-NOFP16-NEXT: fcvt s6, h6
-; CHECK-GI-NOFP16-NEXT: fcvt s7, h7
-; CHECK-GI-NOFP16-NEXT: fabs s16, s2
-; CHECK-GI-NOFP16-NEXT: fabs s17, s3
-; CHECK-GI-NOFP16-NEXT: fcvt h2, s4
-; CHECK-GI-NOFP16-NEXT: fcvt h3, s5
-; CHECK-GI-NOFP16-NEXT: fabs s6, s6
-; CHECK-GI-NOFP16-NEXT: fabs s7, s7
-; CHECK-GI-NOFP16-NEXT: fcvt h4, s16
-; CHECK-GI-NOFP16-NEXT: fcvt h5, s17
-; CHECK-GI-NOFP16-NEXT: fcvt s16, h18
-; CHECK-GI-NOFP16-NEXT: fcvt s17, h19
-; CHECK-GI-NOFP16-NEXT: mov h18, v1.h[4]
-; CHECK-GI-NOFP16-NEXT: mov v2.h[1], v4.h[0]
-; CHECK-GI-NOFP16-NEXT: fcvt h4, s6
-; CHECK-GI-NOFP16-NEXT: mov v3.h[1], v5.h[0]
-; CHECK-GI-NOFP16-NEXT: mov h5, v0.h[4]
-; CHECK-GI-NOFP16-NEXT: fcvt h6, s7
-; CHECK-GI-NOFP16-NEXT: fabs s16, s16
-; CHECK-GI-NOFP16-NEXT: fabs s17, s17
-; CHECK-GI-NOFP16-NEXT: mov h7, v0.h[5]
-; CHECK-GI-NOFP16-NEXT: mov v2.h[2], v4.h[0]
-; CHECK-GI-NOFP16-NEXT: fcvt s18, h18
-; CHECK-GI-NOFP16-NEXT: fcvt s5, h5
-; CHECK-GI-NOFP16-NEXT: mov v3.h[2], v6.h[0]
-; CHECK-GI-NOFP16-NEXT: fcvt h4, s16
-; CHECK-GI-NOFP16-NEXT: fcvt h16, s17
-; CHECK-GI-NOFP16-NEXT: mov h17, v1.h[5]
-; CHECK-GI-NOFP16-NEXT: mov h6, v0.h[6]
-; CHECK-GI-NOFP16-NEXT: fcvt s7, h7
-; CHECK-GI-NOFP16-NEXT: fabs s5, s5
-; CHECK-GI-NOFP16-NEXT: mov v2.h[3], v4.h[0]
-; CHECK-GI-NOFP16-NEXT: mov h4, v1.h[6]
-; CHECK-GI-NOFP16-NEXT: mov v3.h[3], v16.h[0]
-; CHECK-GI-NOFP16-NEXT: fabs s16, s18
-; CHECK-GI-NOFP16-NEXT: fcvt s17, h17
-; CHECK-GI-NOFP16-NEXT: fabs s7, s7
-; CHECK-GI-NOFP16-NEXT: fcvt s6, h6
-; CHECK-GI-NOFP16-NEXT: mov h0, v0.h[7]
-; CHECK-GI-NOFP16-NEXT: mov h1, v1.h[7]
-; CHECK-GI-NOFP16-NEXT: fcvt s4, h4
-; CHECK-GI-NOFP16-NEXT: fcvt h5, s5
-; CHECK-GI-NOFP16-NEXT: fcvt h16, s16
-; CHECK-GI-NOFP16-NEXT: fabs s17, s17
-; CHECK-GI-NOFP16-NEXT: fcvt h7, s7
-; CHECK-GI-NOFP16-NEXT: fabs s6, s6
-; CHECK-GI-NOFP16-NEXT: fcvt s0, h0
-; CHECK-GI-NOFP16-NEXT: fabs s4, s4
-; CHECK-GI-NOFP16-NEXT: fcvt s1, h1
-; CHECK-GI-NOFP16-NEXT: mov v2.h[4], v5.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v3.h[4], v16.h[0]
-; CHECK-GI-NOFP16-NEXT: fcvt h5, s17
-; CHECK-GI-NOFP16-NEXT: fcvt h6, s6
-; CHECK-GI-NOFP16-NEXT: fabs s0, s0
-; CHECK-GI-NOFP16-NEXT: fcvt h4, s4
-; CHECK-GI-NOFP16-NEXT: fabs s1, s1
-; CHECK-GI-NOFP16-NEXT: mov v2.h[5], v7.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v3.h[5], v5.h[0]
-; CHECK-GI-NOFP16-NEXT: fcvt h0, s0
-; CHECK-GI-NOFP16-NEXT: fcvt h1, s1
-; CHECK-GI-NOFP16-NEXT: mov v2.h[6], v6.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v3.h[6], v4.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v2.h[7], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v3.h[7], v1.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.16b, v2.16b
-; CHECK-GI-NOFP16-NEXT: mov v1.16b, v3.16b
+; CHECK-GI-NOFP16-NEXT: fcvtl v2.4s, v0.4h
+; CHECK-GI-NOFP16-NEXT: fcvtl v3.4s, v1.4h
+; CHECK-GI-NOFP16-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-GI-NOFP16-NEXT: fcvtl2 v1.4s, v1.8h
+; CHECK-GI-NOFP16-NEXT: fabs v2.4s, v2.4s
+; CHECK-GI-NOFP16-NEXT: fabs v3.4s, v3.4s
+; CHECK-GI-NOFP16-NEXT: fabs v4.4s, v0.4s
+; CHECK-GI-NOFP16-NEXT: fabs v5.4s, v1.4s
+; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v2.4s
+; CHECK-GI-NOFP16-NEXT: fcvtn v1.4h, v3.4s
+; CHECK-GI-NOFP16-NEXT: fcvtn2 v0.8h, v4.4s
+; CHECK-GI-NOFP16-NEXT: fcvtn2 v1.8h, v5.4s
; CHECK-GI-NOFP16-NEXT: ret
;
; CHECK-GI-FP16-LABEL: fabs_v16f16:
@@ -499,6 +403,3 @@ declare double @llvm.fabs.f64(double)
declare float @llvm.fabs.f32(float)
declare half @llvm.fabs.f16(half)
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; CHECK-GI: {{.*}}
-; CHECK-SD: {{.*}}
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