[llvm] 6df2c2b - [AArch64] Add a more extensive fabs test. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Sun Aug 6 06:03:03 PDT 2023
Author: David Green
Date: 2023-08-06T14:02:57+01:00
New Revision: 6df2c2b4a2230c7364df9486cc5867f49a059502
URL: https://github.com/llvm/llvm-project/commit/6df2c2b4a2230c7364df9486cc5867f49a059502
DIFF: https://github.com/llvm/llvm-project/commit/6df2c2b4a2230c7364df9486cc5867f49a059502.diff
LOG: [AArch64] Add a more extensive fabs test. NFC
Now covers gisel as well as selection dag, and more types are tested. The
existing tests for combines to fabs are moved to fabs-combine.ll.
Added:
llvm/test/CodeGen/AArch64/fabs-combine.ll
Modified:
llvm/test/CodeGen/AArch64/fabs.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/fabs-combine.ll b/llvm/test/CodeGen/AArch64/fabs-combine.ll
new file mode 100644
index 00000000000000..23bf7a699195f7
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/fabs-combine.ll
@@ -0,0 +1,85 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s
+
+; Test against PR36600: https://bugs.llvm.org/show_bug.cgi?id=36600
+; This is not fabs. If X = -0.0, it should return -0.0 not 0.0.
+
+define double @not_fabs(double %x) #0 {
+; CHECK-LABEL: not_fabs:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fneg d1, d0
+; CHECK-NEXT: fcmp d0, #0.0
+; CHECK-NEXT: fcsel d0, d1, d0, le
+; CHECK-NEXT: ret
+ %cmp = fcmp nnan ole double %x, 0.0
+ %sub = fsub nnan double -0.0, %x
+ %cond = select i1 %cmp, double %sub, double %x
+ ret double %cond
+}
+
+; Try again with
diff erent type, predicate, and compare constant.
+
+define float @still_not_fabs(float %x) #0 {
+; CHECK-LABEL: still_not_fabs:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v1.2s, #128, lsl #24
+; CHECK-NEXT: fneg s2, s0
+; CHECK-NEXT: fcmp s0, s1
+; CHECK-NEXT: fcsel s0, s0, s2, ge
+; CHECK-NEXT: ret
+ %cmp = fcmp nnan oge float %x, -0.0
+ %sub = fsub nnan float -0.0, %x
+ %cond = select i1 %cmp, float %x, float %sub
+ ret float %cond
+}
+
+define float @nabsf(float %a) {
+; CHECK-LABEL: nabsf:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fabs s0, s0
+; CHECK-NEXT: fneg s0, s0
+; CHECK-NEXT: ret
+ %conv = bitcast float %a to i32
+ %and = or i32 %conv, -2147483648
+ %conv1 = bitcast i32 %and to float
+ ret float %conv1
+}
+
+define double @nabsd(double %a) {
+; CHECK-LABEL: nabsd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fabs d0, d0
+; CHECK-NEXT: fneg d0, d0
+; CHECK-NEXT: ret
+ %conv = bitcast double %a to i64
+ %and = or i64 %conv, -9223372036854775808
+ %conv1 = bitcast i64 %and to double
+ ret double %conv1
+}
+
+define <4 x float> @nabsv4f32(<4 x float> %a) {
+; CHECK-LABEL: nabsv4f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.4s, #128, lsl #24
+; CHECK-NEXT: ret
+ %conv = bitcast <4 x float> %a to <4 x i32>
+ %and = or <4 x i32> %conv, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
+ %conv1 = bitcast <4 x i32> %and to <4 x float>
+ ret <4 x float> %conv1
+}
+
+define <2 x double> @nabsv2d64(<2 x double> %a) {
+; CHECK-LABEL: nabsv2d64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov x8, #-9223372036854775808
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: ret
+ %conv = bitcast <2 x double> %a to <2 x i64>
+ %and = or <2 x i64> %conv, <i64 -9223372036854775808, i64 -9223372036854775808>
+ %conv1 = bitcast <2 x i64> %and to <2 x double>
+ ret <2 x double> %conv1
+}
+
+attributes #0 = { "no-nans-fp-math"="true" }
+
diff --git a/llvm/test/CodeGen/AArch64/fabs.ll b/llvm/test/CodeGen/AArch64/fabs.ll
index 23bf7a699195f7..054b9bc6870e4b 100644
--- a/llvm/test/CodeGen/AArch64/fabs.ll
+++ b/llvm/test/CodeGen/AArch64/fabs.ll
@@ -1,85 +1,504 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s
-
-; Test against PR36600: https://bugs.llvm.org/show_bug.cgi?id=36600
-; This is not fabs. If X = -0.0, it should return -0.0 not 0.0.
-
-define double @not_fabs(double %x) #0 {
-; CHECK-LABEL: not_fabs:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fneg d1, d0
-; CHECK-NEXT: fcmp d0, #0.0
-; CHECK-NEXT: fcsel d0, d1, d0, le
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -mtriple=aarch64-none-eabi -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD,CHECK-SD-NOFP16
+; RUN: llc -mtriple=aarch64-none-eabi -mattr=+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD,CHECK-SD-FP16
+; RUN: llc -mtriple=aarch64-none-eabi -global-isel -global-isel-abort=2 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI,CHECK-GI-NOFP16
+; RUN: llc -mtriple=aarch64-none-eabi -mattr=+fullfp16 -global-isel -global-isel-abort=2 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI,CHECK-GI-FP16
+
+; CHECK-GI: warning: Instruction selection used fallback path for fabs_v3f64
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fabs_v4f64
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fabs_v3f32
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fabs_v8f32
+; CHECK-GI-FP16-NEXT: warning: Instruction selection used fallback path for fabs_v16f16
+
+define double @fabs_f64(double %a) {
+; CHECK-LABEL: fabs_f64:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fabs d0, d0
; CHECK-NEXT: ret
- %cmp = fcmp nnan ole double %x, 0.0
- %sub = fsub nnan double -0.0, %x
- %cond = select i1 %cmp, double %sub, double %x
- ret double %cond
+entry:
+ %c = call double @llvm.fabs.f64(double %a)
+ ret double %c
}
-; Try again with
diff erent type, predicate, and compare constant.
+define float @fabs_f32(float %a) {
+; CHECK-LABEL: fabs_f32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fabs s0, s0
+; CHECK-NEXT: ret
+entry:
+ %c = call float @llvm.fabs.f32(float %a)
+ ret float %c
+}
-define float @still_not_fabs(float %x) #0 {
-; CHECK-LABEL: still_not_fabs:
-; CHECK: // %bb.0:
-; CHECK-NEXT: movi v1.2s, #128, lsl #24
-; CHECK-NEXT: fneg s2, s0
-; CHECK-NEXT: fcmp s0, s1
-; CHECK-NEXT: fcsel s0, s0, s2, ge
+define half @fabs_f16(half %a) {
+; CHECK-SD-NOFP16-LABEL: fabs_f16:
+; CHECK-SD-NOFP16: // %bb.0: // %entry
+; CHECK-SD-NOFP16-NEXT: fcvt s0, h0
+; CHECK-SD-NOFP16-NEXT: fabs s0, s0
+; CHECK-SD-NOFP16-NEXT: fcvt h0, s0
+; CHECK-SD-NOFP16-NEXT: ret
+;
+; CHECK-SD-FP16-LABEL: fabs_f16:
+; CHECK-SD-FP16: // %bb.0: // %entry
+; CHECK-SD-FP16-NEXT: fabs h0, h0
+; CHECK-SD-FP16-NEXT: ret
+;
+; CHECK-GI-NOFP16-LABEL: fabs_f16:
+; CHECK-GI-NOFP16: // %bb.0: // %entry
+; CHECK-GI-NOFP16-NEXT: fcvt s0, h0
+; CHECK-GI-NOFP16-NEXT: fabs s0, s0
+; CHECK-GI-NOFP16-NEXT: fcvt h0, s0
+; CHECK-GI-NOFP16-NEXT: ret
+;
+; CHECK-GI-FP16-LABEL: fabs_f16:
+; CHECK-GI-FP16: // %bb.0: // %entry
+; CHECK-GI-FP16-NEXT: fabs h0, h0
+; CHECK-GI-FP16-NEXT: ret
+entry:
+ %c = call half @llvm.fabs.f16(half %a)
+ ret half %c
+}
+
+define <2 x double> @fabs_v2f64(<2 x double> %a) {
+; CHECK-LABEL: fabs_v2f64:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fabs v0.2d, v0.2d
; CHECK-NEXT: ret
- %cmp = fcmp nnan oge float %x, -0.0
- %sub = fsub nnan float -0.0, %x
- %cond = select i1 %cmp, float %x, float %sub
- ret float %cond
+entry:
+ %c = call <2 x double> @llvm.fabs.v2f64(<2 x double> %a)
+ ret <2 x double> %c
}
-define float @nabsf(float %a) {
-; CHECK-LABEL: nabsf:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fabs s0, s0
-; CHECK-NEXT: fneg s0, s0
+define <3 x double> @fabs_v3f64(<3 x double> %a) {
+; CHECK-LABEL: fabs_v3f64:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: // kill: def $d2 killed $d2 def $q2
+; CHECK-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-NEXT: fabs v2.2d, v2.2d
+; CHECK-NEXT: // kill: def $d2 killed $d2 killed $q2
+; CHECK-NEXT: fabs v0.2d, v0.2d
+; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: // kill: def $d1 killed $d1 killed $q1
; CHECK-NEXT: ret
- %conv = bitcast float %a to i32
- %and = or i32 %conv, -2147483648
- %conv1 = bitcast i32 %and to float
- ret float %conv1
+entry:
+ %c = call <3 x double> @llvm.fabs.v3f64(<3 x double> %a)
+ ret <3 x double> %c
}
-define double @nabsd(double %a) {
-; CHECK-LABEL: nabsd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fabs d0, d0
-; CHECK-NEXT: fneg d0, d0
+define <4 x double> @fabs_v4f64(<4 x double> %a) {
+; CHECK-LABEL: fabs_v4f64:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fabs v0.2d, v0.2d
+; CHECK-NEXT: fabs v1.2d, v1.2d
+; CHECK-NEXT: ret
+entry:
+ %c = call <4 x double> @llvm.fabs.v4f64(<4 x double> %a)
+ ret <4 x double> %c
+}
+
+define <2 x float> @fabs_v2f32(<2 x float> %a) {
+; CHECK-LABEL: fabs_v2f32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fabs v0.2s, v0.2s
+; CHECK-NEXT: ret
+entry:
+ %c = call <2 x float> @llvm.fabs.v2f32(<2 x float> %a)
+ ret <2 x float> %c
+}
+
+define <3 x float> @fabs_v3f32(<3 x float> %a) {
+; CHECK-LABEL: fabs_v3f32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fabs v0.4s, v0.4s
; CHECK-NEXT: ret
- %conv = bitcast double %a to i64
- %and = or i64 %conv, -9223372036854775808
- %conv1 = bitcast i64 %and to double
- ret double %conv1
+entry:
+ %c = call <3 x float> @llvm.fabs.v3f32(<3 x float> %a)
+ ret <3 x float> %c
}
-define <4 x float> @nabsv4f32(<4 x float> %a) {
-; CHECK-LABEL: nabsv4f32:
-; CHECK: // %bb.0:
-; CHECK-NEXT: orr v0.4s, #128, lsl #24
+define <4 x float> @fabs_v4f32(<4 x float> %a) {
+; CHECK-LABEL: fabs_v4f32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fabs v0.4s, v0.4s
; CHECK-NEXT: ret
- %conv = bitcast <4 x float> %a to <4 x i32>
- %and = or <4 x i32> %conv, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
- %conv1 = bitcast <4 x i32> %and to <4 x float>
- ret <4 x float> %conv1
+entry:
+ %c = call <4 x float> @llvm.fabs.v4f32(<4 x float> %a)
+ ret <4 x float> %c
}
-define <2 x double> @nabsv2d64(<2 x double> %a) {
-; CHECK-LABEL: nabsv2d64:
-; CHECK: // %bb.0:
-; CHECK-NEXT: mov x8, #-9223372036854775808
-; CHECK-NEXT: dup v1.2d, x8
-; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
+define <8 x float> @fabs_v8f32(<8 x float> %a) {
+; CHECK-LABEL: fabs_v8f32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fabs v0.4s, v0.4s
+; CHECK-NEXT: fabs v1.4s, v1.4s
; CHECK-NEXT: ret
- %conv = bitcast <2 x double> %a to <2 x i64>
- %and = or <2 x i64> %conv, <i64 -9223372036854775808, i64 -9223372036854775808>
- %conv1 = bitcast <2 x i64> %and to <2 x double>
- ret <2 x double> %conv1
+entry:
+ %c = call <8 x float> @llvm.fabs.v8f32(<8 x float> %a)
+ ret <8 x float> %c
+}
+
+define <4 x half> @fabs_v4f16(<4 x half> %a) {
+; CHECK-SD-NOFP16-LABEL: fabs_v4f16:
+; CHECK-SD-NOFP16: // %bb.0: // %entry
+; CHECK-SD-NOFP16-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-NOFP16-NEXT: mov h1, v0.h[1]
+; CHECK-SD-NOFP16-NEXT: fcvt s2, h0
+; CHECK-SD-NOFP16-NEXT: mov h3, v0.h[2]
+; CHECK-SD-NOFP16-NEXT: mov h4, v0.h[3]
+; CHECK-SD-NOFP16-NEXT: fcvt s1, h1
+; CHECK-SD-NOFP16-NEXT: fabs s2, s2
+; CHECK-SD-NOFP16-NEXT: fcvt s3, h3
+; CHECK-SD-NOFP16-NEXT: fabs s1, s1
+; CHECK-SD-NOFP16-NEXT: fcvt h0, s2
+; CHECK-SD-NOFP16-NEXT: fcvt s2, h4
+; CHECK-SD-NOFP16-NEXT: fabs s3, s3
+; CHECK-SD-NOFP16-NEXT: fcvt h1, s1
+; CHECK-SD-NOFP16-NEXT: fabs s2, s2
+; CHECK-SD-NOFP16-NEXT: mov v0.h[1], v1.h[0]
+; CHECK-SD-NOFP16-NEXT: fcvt h1, s3
+; CHECK-SD-NOFP16-NEXT: mov v0.h[2], v1.h[0]
+; CHECK-SD-NOFP16-NEXT: fcvt h1, s2
+; CHECK-SD-NOFP16-NEXT: mov v0.h[3], v1.h[0]
+; CHECK-SD-NOFP16-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-SD-NOFP16-NEXT: ret
+;
+; CHECK-SD-FP16-LABEL: fabs_v4f16:
+; CHECK-SD-FP16: // %bb.0: // %entry
+; CHECK-SD-FP16-NEXT: fabs v0.4h, v0.4h
+; CHECK-SD-FP16-NEXT: ret
+;
+; CHECK-GI-NOFP16-LABEL: fabs_v4f16:
+; CHECK-GI-NOFP16: // %bb.0: // %entry
+; CHECK-GI-NOFP16-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NOFP16-NEXT: mov h1, v0.h[1]
+; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[2]
+; CHECK-GI-NOFP16-NEXT: fcvt s3, h0
+; CHECK-GI-NOFP16-NEXT: mov h0, v0.h[3]
+; CHECK-GI-NOFP16-NEXT: fcvt s1, h1
+; CHECK-GI-NOFP16-NEXT: fcvt s2, h2
+; CHECK-GI-NOFP16-NEXT: fabs s3, s3
+; CHECK-GI-NOFP16-NEXT: fcvt s4, h0
+; CHECK-GI-NOFP16-NEXT: fabs s1, s1
+; CHECK-GI-NOFP16-NEXT: fabs s2, s2
+; CHECK-GI-NOFP16-NEXT: fcvt h0, s3
+; CHECK-GI-NOFP16-NEXT: fabs s3, s4
+; CHECK-GI-NOFP16-NEXT: fcvt h1, s1
+; CHECK-GI-NOFP16-NEXT: fcvt h2, s2
+; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v1.h[0]
+; CHECK-GI-NOFP16-NEXT: fcvt h1, s3
+; CHECK-GI-NOFP16-NEXT: mov v0.h[2], v2.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v0.h[3], v1.h[0]
+; CHECK-GI-NOFP16-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NOFP16-NEXT: ret
+;
+; CHECK-GI-FP16-LABEL: fabs_v4f16:
+; CHECK-GI-FP16: // %bb.0: // %entry
+; CHECK-GI-FP16-NEXT: fabs v0.4h, v0.4h
+; CHECK-GI-FP16-NEXT: ret
+entry:
+ %c = call <4 x half> @llvm.fabs.v4f16(<4 x half> %a)
+ ret <4 x half> %c
+}
+
+define <8 x half> @fabs_v8f16(<8 x half> %a) {
+; CHECK-SD-NOFP16-LABEL: fabs_v8f16:
+; CHECK-SD-NOFP16: // %bb.0: // %entry
+; CHECK-SD-NOFP16-NEXT: mov h1, v0.h[1]
+; CHECK-SD-NOFP16-NEXT: mov h2, v0.h[2]
+; CHECK-SD-NOFP16-NEXT: fcvt s3, h0
+; CHECK-SD-NOFP16-NEXT: mov h4, v0.h[3]
+; CHECK-SD-NOFP16-NEXT: fcvt s1, h1
+; CHECK-SD-NOFP16-NEXT: fcvt s2, h2
+; CHECK-SD-NOFP16-NEXT: fabs s3, s3
+; CHECK-SD-NOFP16-NEXT: fcvt s4, h4
+; CHECK-SD-NOFP16-NEXT: fabs s5, s1
+; CHECK-SD-NOFP16-NEXT: fabs s2, s2
+; CHECK-SD-NOFP16-NEXT: fcvt h1, s3
+; CHECK-SD-NOFP16-NEXT: fabs s4, s4
+; CHECK-SD-NOFP16-NEXT: fcvt h3, s5
+; CHECK-SD-NOFP16-NEXT: mov h5, v0.h[4]
+; CHECK-SD-NOFP16-NEXT: fcvt h2, s2
+; CHECK-SD-NOFP16-NEXT: mov v1.h[1], v3.h[0]
+; CHECK-SD-NOFP16-NEXT: mov h3, v0.h[5]
+; CHECK-SD-NOFP16-NEXT: fcvt s5, h5
+; CHECK-SD-NOFP16-NEXT: mov v1.h[2], v2.h[0]
+; CHECK-SD-NOFP16-NEXT: fcvt h2, s4
+; CHECK-SD-NOFP16-NEXT: fcvt s3, h3
+; CHECK-SD-NOFP16-NEXT: fabs s4, s5
+; CHECK-SD-NOFP16-NEXT: mov v1.h[3], v2.h[0]
+; CHECK-SD-NOFP16-NEXT: mov h2, v0.h[6]
+; CHECK-SD-NOFP16-NEXT: fabs s3, s3
+; CHECK-SD-NOFP16-NEXT: fcvt h4, s4
+; CHECK-SD-NOFP16-NEXT: mov h0, v0.h[7]
+; CHECK-SD-NOFP16-NEXT: fcvt s2, h2
+; CHECK-SD-NOFP16-NEXT: fcvt h3, s3
+; CHECK-SD-NOFP16-NEXT: mov v1.h[4], v4.h[0]
+; CHECK-SD-NOFP16-NEXT: fcvt s0, h0
+; CHECK-SD-NOFP16-NEXT: fabs s2, s2
+; CHECK-SD-NOFP16-NEXT: mov v1.h[5], v3.h[0]
+; CHECK-SD-NOFP16-NEXT: fabs s0, s0
+; CHECK-SD-NOFP16-NEXT: fcvt h2, s2
+; CHECK-SD-NOFP16-NEXT: fcvt h0, s0
+; CHECK-SD-NOFP16-NEXT: mov v1.h[6], v2.h[0]
+; CHECK-SD-NOFP16-NEXT: mov v1.h[7], v0.h[0]
+; CHECK-SD-NOFP16-NEXT: mov v0.16b, v1.16b
+; CHECK-SD-NOFP16-NEXT: ret
+;
+; CHECK-SD-FP16-LABEL: fabs_v8f16:
+; CHECK-SD-FP16: // %bb.0: // %entry
+; CHECK-SD-FP16-NEXT: fabs v0.8h, v0.8h
+; CHECK-SD-FP16-NEXT: ret
+;
+; CHECK-GI-NOFP16-LABEL: fabs_v8f16:
+; CHECK-GI-NOFP16: // %bb.0: // %entry
+; CHECK-GI-NOFP16-NEXT: mov h1, v0.h[1]
+; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[2]
+; CHECK-GI-NOFP16-NEXT: fcvt s3, h0
+; CHECK-GI-NOFP16-NEXT: mov h4, v0.h[3]
+; CHECK-GI-NOFP16-NEXT: mov h6, v0.h[4]
+; CHECK-GI-NOFP16-NEXT: fcvt s1, h1
+; CHECK-GI-NOFP16-NEXT: fcvt s2, h2
+; CHECK-GI-NOFP16-NEXT: fabs s3, s3
+; CHECK-GI-NOFP16-NEXT: fcvt s4, h4
+; CHECK-GI-NOFP16-NEXT: fcvt s6, h6
+; CHECK-GI-NOFP16-NEXT: fabs s5, s1
+; CHECK-GI-NOFP16-NEXT: fabs s2, s2
+; CHECK-GI-NOFP16-NEXT: fcvt h1, s3
+; CHECK-GI-NOFP16-NEXT: fabs s4, s4
+; CHECK-GI-NOFP16-NEXT: fabs s6, s6
+; CHECK-GI-NOFP16-NEXT: fcvt h3, s5
+; CHECK-GI-NOFP16-NEXT: mov h5, v0.h[5]
+; CHECK-GI-NOFP16-NEXT: fcvt h2, s2
+; CHECK-GI-NOFP16-NEXT: fcvt h4, s4
+; CHECK-GI-NOFP16-NEXT: mov v1.h[1], v3.h[0]
+; CHECK-GI-NOFP16-NEXT: mov h3, v0.h[6]
+; CHECK-GI-NOFP16-NEXT: fcvt s5, h5
+; CHECK-GI-NOFP16-NEXT: mov h0, v0.h[7]
+; CHECK-GI-NOFP16-NEXT: mov v1.h[2], v2.h[0]
+; CHECK-GI-NOFP16-NEXT: fcvt s3, h3
+; CHECK-GI-NOFP16-NEXT: fabs s2, s5
+; CHECK-GI-NOFP16-NEXT: fcvt h5, s6
+; CHECK-GI-NOFP16-NEXT: fcvt s0, h0
+; CHECK-GI-NOFP16-NEXT: mov v1.h[3], v4.h[0]
+; CHECK-GI-NOFP16-NEXT: fabs s3, s3
+; CHECK-GI-NOFP16-NEXT: fcvt h2, s2
+; CHECK-GI-NOFP16-NEXT: fabs s0, s0
+; CHECK-GI-NOFP16-NEXT: mov v1.h[4], v5.h[0]
+; CHECK-GI-NOFP16-NEXT: fcvt h3, s3
+; CHECK-GI-NOFP16-NEXT: fcvt h0, s0
+; CHECK-GI-NOFP16-NEXT: mov v1.h[5], v2.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v1.h[6], v3.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v1.h[7], v0.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v0.16b, v1.16b
+; CHECK-GI-NOFP16-NEXT: ret
+;
+; CHECK-GI-FP16-LABEL: fabs_v8f16:
+; CHECK-GI-FP16: // %bb.0: // %entry
+; CHECK-GI-FP16-NEXT: fabs v0.8h, v0.8h
+; CHECK-GI-FP16-NEXT: ret
+entry:
+ %c = call <8 x half> @llvm.fabs.v8f16(<8 x half> %a)
+ ret <8 x half> %c
+}
+
+define <16 x half> @fabs_v16f16(<16 x half> %a) {
+; CHECK-SD-NOFP16-LABEL: fabs_v16f16:
+; CHECK-SD-NOFP16: // %bb.0: // %entry
+; CHECK-SD-NOFP16-NEXT: mov h2, v0.h[1]
+; CHECK-SD-NOFP16-NEXT: mov h3, v1.h[1]
+; CHECK-SD-NOFP16-NEXT: mov h4, v0.h[2]
+; CHECK-SD-NOFP16-NEXT: fcvt s5, h0
+; CHECK-SD-NOFP16-NEXT: fcvt s6, h1
+; CHECK-SD-NOFP16-NEXT: mov h7, v1.h[2]
+; CHECK-SD-NOFP16-NEXT: mov h18, v0.h[3]
+; CHECK-SD-NOFP16-NEXT: fcvt s2, h2
+; CHECK-SD-NOFP16-NEXT: fcvt s3, h3
+; CHECK-SD-NOFP16-NEXT: fcvt s4, h4
+; CHECK-SD-NOFP16-NEXT: fabs s5, s5
+; CHECK-SD-NOFP16-NEXT: fabs s6, s6
+; CHECK-SD-NOFP16-NEXT: fcvt s7, h7
+; CHECK-SD-NOFP16-NEXT: fabs s16, s2
+; CHECK-SD-NOFP16-NEXT: fabs s17, s3
+; CHECK-SD-NOFP16-NEXT: fabs s4, s4
+; CHECK-SD-NOFP16-NEXT: fcvt h2, s5
+; CHECK-SD-NOFP16-NEXT: fcvt h3, s6
+; CHECK-SD-NOFP16-NEXT: fabs s7, s7
+; CHECK-SD-NOFP16-NEXT: fcvt h5, s16
+; CHECK-SD-NOFP16-NEXT: fcvt h6, s17
+; CHECK-SD-NOFP16-NEXT: mov h16, v1.h[3]
+; CHECK-SD-NOFP16-NEXT: fcvt s17, h18
+; CHECK-SD-NOFP16-NEXT: fcvt h4, s4
+; CHECK-SD-NOFP16-NEXT: fcvt h7, s7
+; CHECK-SD-NOFP16-NEXT: mov v2.h[1], v5.h[0]
+; CHECK-SD-NOFP16-NEXT: mov h5, v0.h[4]
+; CHECK-SD-NOFP16-NEXT: mov v3.h[1], v6.h[0]
+; CHECK-SD-NOFP16-NEXT: mov h6, v1.h[4]
+; CHECK-SD-NOFP16-NEXT: fcvt s16, h16
+; CHECK-SD-NOFP16-NEXT: fabs s17, s17
+; CHECK-SD-NOFP16-NEXT: mov v2.h[2], v4.h[0]
+; CHECK-SD-NOFP16-NEXT: mov h4, v0.h[5]
+; CHECK-SD-NOFP16-NEXT: fcvt s5, h5
+; CHECK-SD-NOFP16-NEXT: fcvt s6, h6
+; CHECK-SD-NOFP16-NEXT: fabs s16, s16
+; CHECK-SD-NOFP16-NEXT: mov v3.h[2], v7.h[0]
+; CHECK-SD-NOFP16-NEXT: fcvt h7, s17
+; CHECK-SD-NOFP16-NEXT: fcvt s4, h4
+; CHECK-SD-NOFP16-NEXT: fabs s5, s5
+; CHECK-SD-NOFP16-NEXT: fabs s6, s6
+; CHECK-SD-NOFP16-NEXT: fcvt h16, s16
+; CHECK-SD-NOFP16-NEXT: mov v2.h[3], v7.h[0]
+; CHECK-SD-NOFP16-NEXT: mov h7, v1.h[5]
+; CHECK-SD-NOFP16-NEXT: fabs s4, s4
+; CHECK-SD-NOFP16-NEXT: fcvt h5, s5
+; CHECK-SD-NOFP16-NEXT: fcvt h6, s6
+; CHECK-SD-NOFP16-NEXT: mov v3.h[3], v16.h[0]
+; CHECK-SD-NOFP16-NEXT: fcvt h4, s4
+; CHECK-SD-NOFP16-NEXT: mov v2.h[4], v5.h[0]
+; CHECK-SD-NOFP16-NEXT: mov h5, v0.h[6]
+; CHECK-SD-NOFP16-NEXT: mov v3.h[4], v6.h[0]
+; CHECK-SD-NOFP16-NEXT: fcvt s6, h7
+; CHECK-SD-NOFP16-NEXT: mov h0, v0.h[7]
+; CHECK-SD-NOFP16-NEXT: mov v2.h[5], v4.h[0]
+; CHECK-SD-NOFP16-NEXT: mov h4, v1.h[6]
+; CHECK-SD-NOFP16-NEXT: fcvt s5, h5
+; CHECK-SD-NOFP16-NEXT: fabs s6, s6
+; CHECK-SD-NOFP16-NEXT: mov h1, v1.h[7]
+; CHECK-SD-NOFP16-NEXT: fcvt s0, h0
+; CHECK-SD-NOFP16-NEXT: fcvt s4, h4
+; CHECK-SD-NOFP16-NEXT: fabs s5, s5
+; CHECK-SD-NOFP16-NEXT: fcvt h6, s6
+; CHECK-SD-NOFP16-NEXT: fcvt s1, h1
+; CHECK-SD-NOFP16-NEXT: fabs s0, s0
+; CHECK-SD-NOFP16-NEXT: fabs s4, s4
+; CHECK-SD-NOFP16-NEXT: fcvt h5, s5
+; CHECK-SD-NOFP16-NEXT: mov v3.h[5], v6.h[0]
+; CHECK-SD-NOFP16-NEXT: fabs s1, s1
+; CHECK-SD-NOFP16-NEXT: fcvt h0, s0
+; CHECK-SD-NOFP16-NEXT: fcvt h4, s4
+; CHECK-SD-NOFP16-NEXT: mov v2.h[6], v5.h[0]
+; CHECK-SD-NOFP16-NEXT: fcvt h1, s1
+; CHECK-SD-NOFP16-NEXT: mov v3.h[6], v4.h[0]
+; CHECK-SD-NOFP16-NEXT: mov v2.h[7], v0.h[0]
+; CHECK-SD-NOFP16-NEXT: mov v3.h[7], v1.h[0]
+; CHECK-SD-NOFP16-NEXT: mov v0.16b, v2.16b
+; CHECK-SD-NOFP16-NEXT: mov v1.16b, v3.16b
+; CHECK-SD-NOFP16-NEXT: ret
+;
+; CHECK-SD-FP16-LABEL: fabs_v16f16:
+; CHECK-SD-FP16: // %bb.0: // %entry
+; CHECK-SD-FP16-NEXT: fabs v0.8h, v0.8h
+; CHECK-SD-FP16-NEXT: fabs v1.8h, v1.8h
+; CHECK-SD-FP16-NEXT: ret
+;
+; CHECK-GI-NOFP16-LABEL: fabs_v16f16:
+; CHECK-GI-NOFP16: // %bb.0: // %entry
+; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[1]
+; CHECK-GI-NOFP16-NEXT: mov h3, v1.h[1]
+; CHECK-GI-NOFP16-NEXT: fcvt s4, h0
+; CHECK-GI-NOFP16-NEXT: fcvt s5, h1
+; CHECK-GI-NOFP16-NEXT: mov h6, v0.h[2]
+; CHECK-GI-NOFP16-NEXT: mov h7, v1.h[2]
+; CHECK-GI-NOFP16-NEXT: mov h18, v0.h[3]
+; CHECK-GI-NOFP16-NEXT: mov h19, v1.h[3]
+; CHECK-GI-NOFP16-NEXT: fcvt s2, h2
+; CHECK-GI-NOFP16-NEXT: fcvt s3, h3
+; CHECK-GI-NOFP16-NEXT: fabs s4, s4
+; CHECK-GI-NOFP16-NEXT: fabs s5, s5
+; CHECK-GI-NOFP16-NEXT: fcvt s6, h6
+; CHECK-GI-NOFP16-NEXT: fcvt s7, h7
+; CHECK-GI-NOFP16-NEXT: fabs s16, s2
+; CHECK-GI-NOFP16-NEXT: fabs s17, s3
+; CHECK-GI-NOFP16-NEXT: fcvt h2, s4
+; CHECK-GI-NOFP16-NEXT: fcvt h3, s5
+; CHECK-GI-NOFP16-NEXT: fabs s6, s6
+; CHECK-GI-NOFP16-NEXT: fabs s7, s7
+; CHECK-GI-NOFP16-NEXT: fcvt h4, s16
+; CHECK-GI-NOFP16-NEXT: fcvt h5, s17
+; CHECK-GI-NOFP16-NEXT: fcvt s16, h18
+; CHECK-GI-NOFP16-NEXT: fcvt s17, h19
+; CHECK-GI-NOFP16-NEXT: mov h18, v1.h[4]
+; CHECK-GI-NOFP16-NEXT: mov v2.h[1], v4.h[0]
+; CHECK-GI-NOFP16-NEXT: fcvt h4, s6
+; CHECK-GI-NOFP16-NEXT: mov v3.h[1], v5.h[0]
+; CHECK-GI-NOFP16-NEXT: mov h5, v0.h[4]
+; CHECK-GI-NOFP16-NEXT: fcvt h6, s7
+; CHECK-GI-NOFP16-NEXT: fabs s16, s16
+; CHECK-GI-NOFP16-NEXT: fabs s17, s17
+; CHECK-GI-NOFP16-NEXT: mov h7, v0.h[5]
+; CHECK-GI-NOFP16-NEXT: mov v2.h[2], v4.h[0]
+; CHECK-GI-NOFP16-NEXT: fcvt s18, h18
+; CHECK-GI-NOFP16-NEXT: fcvt s5, h5
+; CHECK-GI-NOFP16-NEXT: mov v3.h[2], v6.h[0]
+; CHECK-GI-NOFP16-NEXT: fcvt h4, s16
+; CHECK-GI-NOFP16-NEXT: fcvt h16, s17
+; CHECK-GI-NOFP16-NEXT: mov h17, v1.h[5]
+; CHECK-GI-NOFP16-NEXT: mov h6, v0.h[6]
+; CHECK-GI-NOFP16-NEXT: fcvt s7, h7
+; CHECK-GI-NOFP16-NEXT: fabs s5, s5
+; CHECK-GI-NOFP16-NEXT: mov v2.h[3], v4.h[0]
+; CHECK-GI-NOFP16-NEXT: mov h4, v1.h[6]
+; CHECK-GI-NOFP16-NEXT: mov v3.h[3], v16.h[0]
+; CHECK-GI-NOFP16-NEXT: fabs s16, s18
+; CHECK-GI-NOFP16-NEXT: fcvt s17, h17
+; CHECK-GI-NOFP16-NEXT: fabs s7, s7
+; CHECK-GI-NOFP16-NEXT: fcvt s6, h6
+; CHECK-GI-NOFP16-NEXT: mov h0, v0.h[7]
+; CHECK-GI-NOFP16-NEXT: mov h1, v1.h[7]
+; CHECK-GI-NOFP16-NEXT: fcvt s4, h4
+; CHECK-GI-NOFP16-NEXT: fcvt h5, s5
+; CHECK-GI-NOFP16-NEXT: fcvt h16, s16
+; CHECK-GI-NOFP16-NEXT: fabs s17, s17
+; CHECK-GI-NOFP16-NEXT: fcvt h7, s7
+; CHECK-GI-NOFP16-NEXT: fabs s6, s6
+; CHECK-GI-NOFP16-NEXT: fcvt s0, h0
+; CHECK-GI-NOFP16-NEXT: fabs s4, s4
+; CHECK-GI-NOFP16-NEXT: fcvt s1, h1
+; CHECK-GI-NOFP16-NEXT: mov v2.h[4], v5.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v3.h[4], v16.h[0]
+; CHECK-GI-NOFP16-NEXT: fcvt h5, s17
+; CHECK-GI-NOFP16-NEXT: fcvt h6, s6
+; CHECK-GI-NOFP16-NEXT: fabs s0, s0
+; CHECK-GI-NOFP16-NEXT: fcvt h4, s4
+; CHECK-GI-NOFP16-NEXT: fabs s1, s1
+; CHECK-GI-NOFP16-NEXT: mov v2.h[5], v7.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v3.h[5], v5.h[0]
+; CHECK-GI-NOFP16-NEXT: fcvt h0, s0
+; CHECK-GI-NOFP16-NEXT: fcvt h1, s1
+; CHECK-GI-NOFP16-NEXT: mov v2.h[6], v6.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v3.h[6], v4.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v2.h[7], v0.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v3.h[7], v1.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v0.16b, v2.16b
+; CHECK-GI-NOFP16-NEXT: mov v1.16b, v3.16b
+; CHECK-GI-NOFP16-NEXT: ret
+;
+; CHECK-GI-FP16-LABEL: fabs_v16f16:
+; CHECK-GI-FP16: // %bb.0: // %entry
+; CHECK-GI-FP16-NEXT: fabs v0.8h, v0.8h
+; CHECK-GI-FP16-NEXT: fabs v1.8h, v1.8h
+; CHECK-GI-FP16-NEXT: ret
+entry:
+ %c = call <16 x half> @llvm.fabs.v16f16(<16 x half> %a)
+ ret <16 x half> %c
}
-attributes #0 = { "no-nans-fp-math"="true" }
+declare <16 x half> @llvm.fabs.v16f16(<16 x half>)
+declare <2 x double> @llvm.fabs.v2f64(<2 x double>)
+declare <2 x float> @llvm.fabs.v2f32(<2 x float>)
+declare <3 x double> @llvm.fabs.v3f64(<3 x double>)
+declare <3 x float> @llvm.fabs.v3f32(<3 x float>)
+declare <4 x double> @llvm.fabs.v4f64(<4 x double>)
+declare <4 x float> @llvm.fabs.v4f32(<4 x float>)
+declare <4 x half> @llvm.fabs.v4f16(<4 x half>)
+declare <8 x float> @llvm.fabs.v8f32(<8 x float>)
+declare <8 x half> @llvm.fabs.v8f16(<8 x half>)
+declare double @llvm.fabs.f64(double)
+declare float @llvm.fabs.f32(float)
+declare half @llvm.fabs.f16(half)
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK-GI: {{.*}}
+; CHECK-SD: {{.*}}
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