[llvm] c15e7bb - [RISCV] Add explicit i64 to an isel pattern that is only valid for RV64. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-08-04T23:42:13-07:00
New Revision: c15e7bb97d2e3fcb682b8e32fef68e3674e58a7e

URL: https://github.com/llvm/llvm-project/commit/c15e7bb97d2e3fcb682b8e32fef68e3674e58a7e
DIFF: https://github.com/llvm/llvm-project/commit/c15e7bb97d2e3fcb682b8e32fef68e3674e58a7e.diff

LOG: [RISCV] Add explicit i64 to an isel pattern that is only valid for RV64. NFC

This stops tablegen from generating an unneeded pattern checking for
an i32 type.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfo.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 1dbb3832bb6045..4af8457e913c4c 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1906,7 +1906,7 @@ let Predicates = [IsRV64], Uses = [X5],
     Defs = [X1, X6, X7, X28, X29, X30, X31] in
 def HWASAN_CHECK_MEMACCESS_SHORTGRANULES 
   : Pseudo<(outs), (ins GPRJALR:$ptr, i32imm:$accessinfo),
-           [(int_hwasan_check_memaccess_shortgranules X5, GPRJALR:$ptr,
+           [(int_hwasan_check_memaccess_shortgranules (i64 X5), GPRJALR:$ptr,
                                                       (i32 timm:$accessinfo))]>;
 
 // This gets lowered into a 20-byte instruction sequence (at most)