[PATCH] D156777: [SelectionDAG] Add/Improve cases in `isKnownNeverZero`

[Noah Goldstein via Phabricator via llvm-commits]

goldstein.w.n added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:5119
+    if (MaxCnt.ule(ValKnown.getBitWidth()) &&
+        !ValKnown.One.shl(MaxCnt).isZero())
       return true;
----------------
RKSimon wrote:
> goldstein.w.n wrote:
> > RKSimon wrote:
> > > Use isNonZero() instead?
> > apint doens't have `isNonZero`.
> I missed that! Would it improve the analysis if we used ValKnown.shl(CntKnown).isNonZero() instead?
I don't think so. Known bits needs to actually figure out which is set. I.e if we have:
`2 << (x & 7)`, known bits won't be able to set anything as it doesn't know any ones (value can be 2, 4, 8,...256 but there are no overlapping bits none can be set), whereas this logic still allows us to prove non-zero.


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156777/new/

https://reviews.llvm.org/D156777