[PATCH] D152828: [MachineSink][AArch64] Sink instruction copies when they can replace copy into hard register or folded into addressing mode

[Momchil Velikov via Phabricator via llvm-commits]

chill added a comment.

In D152828#4528166 <https://reviews.llvm.org/D152828#4528166>, @dmgreen wrote:

> High level comment - I like having the ability to do this, is there a reason it is a sink, as opposed to a peephole? I think a lot of the time it may just always be profitable to combine into address operands or add+lsl. Is it due to the register pressure?

Yes, I think we should take register pressure into account, as we can replace use of one register with a use of two registers (e.g. `ldr Xd, [Xa]` -> `ldr Xd, [Xn, Xm]`).


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https://reviews.llvm.org/D152828