[PATCH] D156777: [SelectionDAG] Add/Improve cases in `isKnownNeverZero`

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:5118
+    APInt MaxCnt = computeKnownBits(Op.getOperand(1), Depth + 1).getMaxValue();
+    if (MaxCnt.ule(ValKnown.getBitWidth()) &&
+        !ValKnown.One.shl(MaxCnt).isZero())
----------------
ult? - shift by bitwidth is undefined.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156777/new/

https://reviews.llvm.org/D156777