[llvm] f3b9b94 - [AArch64][GISel] Expand arm64-dup and arm64-rev tests for global isel. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 4 01:06:52 PDT 2023
Author: David Green
Date: 2023-08-04T09:06:47+01:00
New Revision: f3b9b94a8b4114ba4aa2517f4cffc58e6219609d
URL: https://github.com/llvm/llvm-project/commit/f3b9b94a8b4114ba4aa2517f4cffc58e6219609d
DIFF: https://github.com/llvm/llvm-project/commit/f3b9b94a8b4114ba4aa2517f4cffc58e6219609d.diff
LOG: [AArch64][GISel] Expand arm64-dup and arm64-rev tests for global isel. NFC
Added:
Modified:
llvm/test/CodeGen/AArch64/arm64-dup.ll
llvm/test/CodeGen/AArch64/arm64-rev.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/arm64-dup.ll b/llvm/test/CodeGen/AArch64/arm64-dup.ll
index 0fdb60cc08b0e6..75e6aa1f19bfd0 100644
--- a/llvm/test/CodeGen/AArch64/arm64-dup.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-dup.ll
@@ -1,5 +1,13 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
+; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
+
+; CHECK-GI: warning: Instruction selection used fallback path for v_shuffledup8
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for v_shuffledup16
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for vduplane8
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for vduplane16
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_perfectshuffle_dupext_v4i16
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_perfectshuffle_dupext_v4f16
define <8 x i8> @v_dup8(i8 %A) nounwind {
; CHECK-LABEL: v_dup8:
@@ -365,10 +373,19 @@ define <2 x i64> @h(i64 %a, i64 %b) nounwind readnone {
;
; *However*, it is a dup vD.4h, vN.h[2*idx].
define <4 x i16> @test_build_illegal(<4 x i32> %in) {
-; CHECK-LABEL: test_build_illegal:
-; CHECK: // %bb.0:
-; CHECK-NEXT: dup.4h v0, v0[6]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_build_illegal:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: dup.4h v0, v0[6]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_build_illegal:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov.h v1[1], v0[0]
+; CHECK-GI-NEXT: mov s0, v0[3]
+; CHECK-GI-NEXT: mov.h v1[2], v0[0]
+; CHECK-GI-NEXT: mov.h v1[3], v0[0]
+; CHECK-GI-NEXT: fmov d0, d1
+; CHECK-GI-NEXT: ret
%val = extractelement <4 x i32> %in, i32 3
%smallval = trunc i32 %val to i16
%vec = insertelement <4x i16> undef, i16 %smallval, i32 3
@@ -380,10 +397,16 @@ define <4 x i16> @test_build_illegal(<4 x i32> %in) {
; SelectionDAGBuilder here. We then added a DUPLANE on top of that, preventing
; the formation of an indexed-by-7 MLS.
define <4 x i16> @test_high_splat(<4 x i16> %a, <4 x i16> %b, <8 x i16> %v) #0 {
-; CHECK-LABEL: test_high_splat:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: mls.4h v0, v1, v2[7]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_high_splat:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: mls.4h v0, v1, v2[7]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_high_splat:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: dup.8h v2, v2[7]
+; CHECK-GI-NEXT: mls.4h v0, v2, v1
+; CHECK-GI-NEXT: ret
entry:
%shuffle = shufflevector <8 x i16> %v, <8 x i16> undef, <4 x i32> <i32 7, i32 7, i32 7, i32 7>
%mul = mul <4 x i16> %shuffle, %b
@@ -418,34 +441,65 @@ define <4 x half> @test_perfectshuffle_dupext_v4f16(<4 x half> %a, <4 x half> %b
}
define <4 x i32> @test_perfectshuffle_dupext_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind {
-; CHECK-LABEL: test_perfectshuffle_dupext_v4i32:
-; CHECK: // %bb.0:
-; CHECK-NEXT: trn1.4s v0, v0, v0
-; CHECK-NEXT: mov.d v0[1], v1[0]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_perfectshuffle_dupext_v4i32:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: trn1.4s v0, v0, v0
+; CHECK-SD-NEXT: mov.d v0[1], v1[0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_perfectshuffle_dupext_v4i32:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: adrp x8, .LCPI35_0
+; CHECK-GI-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; CHECK-GI-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI35_0]
+; CHECK-GI-NEXT: tbl.16b v0, { v0, v1 }, v2
+; CHECK-GI-NEXT: ret
%r = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 0, i32 4, i32 5>
ret <4 x i32> %r
}
define <4 x float> @test_perfectshuffle_dupext_v4f32(<4 x float> %a, <4 x float> %b) nounwind {
-; CHECK-LABEL: test_perfectshuffle_dupext_v4f32:
-; CHECK: // %bb.0:
-; CHECK-NEXT: trn1.4s v0, v0, v0
-; CHECK-NEXT: mov.d v0[1], v1[0]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_perfectshuffle_dupext_v4f32:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: trn1.4s v0, v0, v0
+; CHECK-SD-NEXT: mov.d v0[1], v1[0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_perfectshuffle_dupext_v4f32:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: adrp x8, .LCPI36_0
+; CHECK-GI-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; CHECK-GI-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI36_0]
+; CHECK-GI-NEXT: tbl.16b v0, { v0, v1 }, v2
+; CHECK-GI-NEXT: ret
%r = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 0, i32 4, i32 5>
ret <4 x float> %r
}
define void @disguised_dup(<4 x float> %x, ptr %p1, ptr %p2) {
-; CHECK-LABEL: disguised_dup:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ext.16b v1, v0, v0, #4
-; CHECK-NEXT: mov.s v1[2], v0[0]
-; CHECK-NEXT: dup.4s v0, v0[0]
-; CHECK-NEXT: str q1, [x0]
-; CHECK-NEXT: str q0, [x1]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: disguised_dup:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ext.16b v1, v0, v0, #4
+; CHECK-SD-NEXT: mov.s v1[2], v0[0]
+; CHECK-SD-NEXT: dup.4s v0, v0[0]
+; CHECK-SD-NEXT: str q1, [x0]
+; CHECK-SD-NEXT: str q0, [x1]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: disguised_dup:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: adrp x8, .LCPI37_1
+; CHECK-GI-NEXT: // kill: def $q0 killed $q0 def $q0_q1
+; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI37_1]
+; CHECK-GI-NEXT: adrp x8, .LCPI37_0
+; CHECK-GI-NEXT: tbl.16b v0, { v0, v1 }, v2
+; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI37_0]
+; CHECK-GI-NEXT: tbl.16b v2, { v0, v1 }, v2
+; CHECK-GI-NEXT: str q0, [x0]
+; CHECK-GI-NEXT: str q2, [x1]
+; CHECK-GI-NEXT: ret
%shuf = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 1, i32 2, i32 0, i32 0>
%dup = shufflevector <4 x float> %shuf, <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 2, i32 3>
store <4 x float> %shuf, ptr %p1, align 8
@@ -454,42 +508,71 @@ define void @disguised_dup(<4 x float> %x, ptr %p1, ptr %p2) {
}
define <2 x i32> @dup_const2(<2 x i32> %A) nounwind {
-; CHECK-LABEL: dup_const2:
-; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #32770
-; CHECK-NEXT: movk w8, #128, lsl #16
-; CHECK-NEXT: dup.2s v1, w8
-; CHECK-NEXT: add.2s v0, v0, v1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: dup_const2:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov w8, #32770 // =0x8002
+; CHECK-SD-NEXT: movk w8, #128, lsl #16
+; CHECK-SD-NEXT: dup.2s v1, w8
+; CHECK-SD-NEXT: add.2s v0, v0, v1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: dup_const2:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: adrp x8, .LCPI38_0
+; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI38_0]
+; CHECK-GI-NEXT: add.2s v0, v0, v1
+; CHECK-GI-NEXT: ret
%tmp2 = add <2 x i32> %A, <i32 8421378, i32 8421378>
ret <2 x i32> %tmp2
}
define <2 x i32> @dup_const4_ext(<4 x i32> %A) nounwind {
-; CHECK-LABEL: dup_const4_ext:
-; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #32769
-; CHECK-NEXT: movk w8, #128, lsl #16
-; CHECK-NEXT: dup.2s v1, w8
-; CHECK-NEXT: add.2s v0, v0, v1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: dup_const4_ext:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov w8, #32769 // =0x8001
+; CHECK-SD-NEXT: movk w8, #128, lsl #16
+; CHECK-SD-NEXT: dup.2s v1, w8
+; CHECK-SD-NEXT: add.2s v0, v0, v1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: dup_const4_ext:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: adrp x8, .LCPI39_0
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI39_0]
+; CHECK-GI-NEXT: add.4s v0, v0, v1
+; CHECK-GI-NEXT: ext.16b v0, v0, v0, #0
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: ret
%tmp1 = add <4 x i32> %A, <i32 8421377, i32 8421377, i32 8421377, i32 8421377>
%tmp2 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
ret <2 x i32> %tmp2
}
define <4 x i32> @dup_const24(<2 x i32> %A, <2 x i32> %B, <4 x i32> %C) nounwind {
-; CHECK-LABEL: dup_const24:
-; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #32768
-; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-NEXT: movk w8, #128, lsl #16
-; CHECK-NEXT: dup.4s v3, w8
-; CHECK-NEXT: add.2s v0, v0, v3
-; CHECK-NEXT: mov.d v0[1], v1[0]
-; CHECK-NEXT: add.4s v1, v2, v3
-; CHECK-NEXT: eor.16b v0, v1, v0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: dup_const24:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov w8, #32768 // =0x8000
+; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-SD-NEXT: movk w8, #128, lsl #16
+; CHECK-SD-NEXT: dup.4s v3, w8
+; CHECK-SD-NEXT: add.2s v0, v0, v3
+; CHECK-SD-NEXT: mov.d v0[1], v1[0]
+; CHECK-SD-NEXT: add.4s v1, v2, v3
+; CHECK-SD-NEXT: eor.16b v0, v1, v0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: dup_const24:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: adrp x8, .LCPI40_1
+; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-GI-NEXT: ldr d3, [x8, :lo12:.LCPI40_1]
+; CHECK-GI-NEXT: adrp x8, .LCPI40_0
+; CHECK-GI-NEXT: add.2s v0, v0, v3
+; CHECK-GI-NEXT: ldr q3, [x8, :lo12:.LCPI40_0]
+; CHECK-GI-NEXT: mov.d v0[1], v1[0]
+; CHECK-GI-NEXT: add.4s v1, v2, v3
+; CHECK-GI-NEXT: eor.16b v0, v1, v0
+; CHECK-GI-NEXT: ret
%tmp1 = add <2 x i32> %A, <i32 8421376, i32 8421376>
%tmp4 = shufflevector <2 x i32> %tmp1, <2 x i32> %B, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%tmp3 = add <4 x i32> %C, <i32 8421376, i32 8421376, i32 8421376, i32 8421376>
@@ -498,10 +581,16 @@ define <4 x i32> @dup_const24(<2 x i32> %A, <2 x i32> %B, <4 x i32> %C) nounwind
}
define <8 x i16> @bitcast_i64_v8i16(i64 %a) {
-; CHECK-LABEL: bitcast_i64_v8i16:
-; CHECK: // %bb.0:
-; CHECK-NEXT: dup.8h v0, w0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: bitcast_i64_v8i16:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: dup.8h v0, w0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: bitcast_i64_v8i16:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: fmov d0, x0
+; CHECK-GI-NEXT: dup.8h v0, v0[0]
+; CHECK-GI-NEXT: ret
%b = bitcast i64 %a to <4 x i16>
%r = shufflevector <4 x i16> %b, <4 x i16> poison, <8 x i32> zeroinitializer
ret <8 x i16> %r
@@ -541,11 +630,16 @@ define <8 x half> @bitcast_i64_v8f16(i64 %a) {
}
define <2 x i64> @bitcast_i64_v2f64(i64 %a) {
-; CHECK-LABEL: bitcast_i64_v2f64:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fmov d0, x0
-; CHECK-NEXT: dup.2d v0, v0[0]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: bitcast_i64_v2f64:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: fmov d0, x0
+; CHECK-SD-NEXT: dup.2d v0, v0[0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: bitcast_i64_v2f64:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: dup.2d v0, x0
+; CHECK-GI-NEXT: ret
%b = bitcast i64 %a to <1 x i64>
%r = shufflevector <1 x i64> %b, <1 x i64> poison, <2 x i32> zeroinitializer
ret <2 x i64> %r
diff --git a/llvm/test/CodeGen/AArch64/arm64-rev.ll b/llvm/test/CodeGen/AArch64/arm64-rev.ll
index 90f937afb5a636..0081a28ab10fda 100644
--- a/llvm/test/CodeGen/AArch64/arm64-rev.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-rev.ll
@@ -1,34 +1,29 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=aarch64-eabi -aarch64-neon-syntax=apple | FileCheck %s
-; RUN: llc < %s -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel* -mtriple=aarch64-eabi -aarch64-neon-syntax=apple 2>&1 | FileCheck %s --check-prefixes=GISEL
+; RUN: llc < %s -mtriple=aarch64-eabi -aarch64-neon-syntax=apple | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -mtriple=aarch64-eabi -aarch64-neon-syntax=apple -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
+
+; CHECK-GI: warning: Instruction selection used fallback path for test_vrev64D8
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_vrev64D16
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_vrev32D8
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_vrev32D16
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_vrev16D8
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_vrev64D8_undef
-; GISEL-NOT: remark{{.*}}test_rev_w
define i32 @test_rev_w(i32 %a) nounwind {
; CHECK-LABEL: test_rev_w:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: rev w0, w0
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test_rev_w:
-; GISEL: // %bb.0: // %entry
-; GISEL-NEXT: rev w0, w0
-; GISEL-NEXT: ret
entry:
%0 = tail call i32 @llvm.bswap.i32(i32 %a)
ret i32 %0
}
-; GISEL-NOT: remark{{.*}}test_rev_x
define i64 @test_rev_x(i64 %a) nounwind {
; CHECK-LABEL: test_rev_x:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: rev x0, x0
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test_rev_x:
-; GISEL: // %bb.0: // %entry
-; GISEL-NEXT: rev x0, x0
-; GISEL-NEXT: ret
entry:
%0 = tail call i64 @llvm.bswap.i64(i64 %a)
ret i64 %0
@@ -37,18 +32,18 @@ entry:
; Canonicalize (srl (bswap x), 16) to (rotr (bswap x), 16) if the high 16-bits
; of %a are zero. This optimizes rev + lsr 16 to rev16.
define i32 @test_rev_w_srl16(i16 %a) {
-; CHECK-LABEL: test_rev_w_srl16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: rev w8, w0
-; CHECK-NEXT: lsr w0, w8, #16
-; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test_rev_w_srl16:
-; GISEL: // %bb.0: // %entry
-; GISEL-NEXT: and w8, w0, #0xffff
-; GISEL-NEXT: rev w8, w8
-; GISEL-NEXT: lsr w0, w8, #16
-; GISEL-NEXT: ret
+; CHECK-SD-LABEL: test_rev_w_srl16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: rev w8, w0
+; CHECK-SD-NEXT: lsr w0, w8, #16
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_rev_w_srl16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: and w8, w0, #0xffff
+; CHECK-GI-NEXT: rev w8, w8
+; CHECK-GI-NEXT: lsr w0, w8, #16
+; CHECK-GI-NEXT: ret
entry:
%0 = zext i16 %a to i32
%1 = tail call i32 @llvm.bswap.i32(i32 %0)
@@ -63,13 +58,6 @@ define i32 @test_rev_w_srl16_load(ptr %a) {
; CHECK-NEXT: rev w8, w8
; CHECK-NEXT: lsr w0, w8, #16
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test_rev_w_srl16_load:
-; GISEL: // %bb.0: // %entry
-; GISEL-NEXT: ldrh w8, [x0]
-; GISEL-NEXT: rev w8, w8
-; GISEL-NEXT: lsr w0, w8, #16
-; GISEL-NEXT: ret
entry:
%0 = load i16, ptr %a
%1 = zext i16 %0 to i32
@@ -79,20 +67,20 @@ entry:
}
define i32 @test_rev_w_srl16_add(i8 %a, i8 %b) {
-; CHECK-LABEL: test_rev_w_srl16_add:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: and w8, w0, #0xff
-; CHECK-NEXT: add w8, w8, w1, uxtb
-; CHECK-NEXT: rev16 w0, w8
-; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test_rev_w_srl16_add:
-; GISEL: // %bb.0: // %entry
-; GISEL-NEXT: and w8, w1, #0xff
-; GISEL-NEXT: add w8, w8, w0, uxtb
-; GISEL-NEXT: rev w8, w8
-; GISEL-NEXT: lsr w0, w8, #16
-; GISEL-NEXT: ret
+; CHECK-SD-LABEL: test_rev_w_srl16_add:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: and w8, w0, #0xff
+; CHECK-SD-NEXT: add w8, w8, w1, uxtb
+; CHECK-SD-NEXT: rev16 w0, w8
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_rev_w_srl16_add:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: and w8, w1, #0xff
+; CHECK-GI-NEXT: add w8, w8, w0, uxtb
+; CHECK-GI-NEXT: rev w8, w8
+; CHECK-GI-NEXT: lsr w0, w8, #16
+; CHECK-GI-NEXT: ret
entry:
%0 = zext i8 %a to i32
%1 = zext i8 %b to i32
@@ -105,19 +93,19 @@ entry:
; Canonicalize (srl (bswap x), 32) to (rotr (bswap x), 32) if the high 32-bits
; of %a are zero. This optimizes rev + lsr 32 to rev32.
define i64 @test_rev_x_srl32(i32 %a) {
-; CHECK-LABEL: test_rev_x_srl32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
-; CHECK-NEXT: rev x8, x0
-; CHECK-NEXT: lsr x0, x8, #32
-; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test_rev_x_srl32:
-; GISEL: // %bb.0: // %entry
-; GISEL-NEXT: mov w8, w0
-; GISEL-NEXT: rev x8, x8
-; GISEL-NEXT: lsr x0, x8, #32
-; GISEL-NEXT: ret
+; CHECK-SD-LABEL: test_rev_x_srl32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x0
+; CHECK-SD-NEXT: rev x8, x0
+; CHECK-SD-NEXT: lsr x0, x8, #32
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_rev_x_srl32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: mov w8, w0
+; CHECK-GI-NEXT: rev x8, x8
+; CHECK-GI-NEXT: lsr x0, x8, #32
+; CHECK-GI-NEXT: ret
entry:
%0 = zext i32 %a to i64
%1 = tail call i64 @llvm.bswap.i64(i64 %0)
@@ -132,13 +120,6 @@ define i64 @test_rev_x_srl32_load(ptr %a) {
; CHECK-NEXT: rev x8, x8
; CHECK-NEXT: lsr x0, x8, #32
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test_rev_x_srl32_load:
-; GISEL: // %bb.0: // %entry
-; GISEL-NEXT: ldr w8, [x0]
-; GISEL-NEXT: rev x8, x8
-; GISEL-NEXT: lsr x0, x8, #32
-; GISEL-NEXT: ret
entry:
%0 = load i32, ptr %a
%1 = zext i32 %0 to i64
@@ -148,18 +129,18 @@ entry:
}
define i64 @test_rev_x_srl32_shift(i64 %a) {
-; CHECK-LABEL: test_rev_x_srl32_shift:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ubfx x8, x0, #2, #29
-; CHECK-NEXT: rev32 x0, x8
-; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test_rev_x_srl32_shift:
-; GISEL: // %bb.0: // %entry
-; GISEL-NEXT: ubfx x8, x0, #2, #29
-; GISEL-NEXT: rev x8, x8
-; GISEL-NEXT: lsr x0, x8, #32
-; GISEL-NEXT: ret
+; CHECK-SD-LABEL: test_rev_x_srl32_shift:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: ubfx x8, x0, #2, #29
+; CHECK-SD-NEXT: rev32 x0, x8
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_rev_x_srl32_shift:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: ubfx x8, x0, #2, #29
+; CHECK-GI-NEXT: rev x8, x8
+; CHECK-GI-NEXT: lsr x0, x8, #32
+; CHECK-GI-NEXT: ret
entry:
%0 = shl i64 %a, 33
%1 = lshr i64 %0, 35
@@ -172,23 +153,23 @@ declare i32 @llvm.bswap.i32(i32) nounwind readnone
declare i64 @llvm.bswap.i64(i64) nounwind readnone
define i32 @test_rev16_w(i32 %X) nounwind {
-; CHECK-LABEL: test_rev16_w:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: rev16 w0, w0
-; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test_rev16_w:
-; GISEL: // %bb.0: // %entry
-; GISEL-NEXT: lsr w8, w0, #8
-; GISEL-NEXT: lsl w9, w0, #8
-; GISEL-NEXT: and w10, w8, #0xff0000
-; GISEL-NEXT: and w11, w9, #0xff000000
-; GISEL-NEXT: and w8, w8, #0xff
-; GISEL-NEXT: and w9, w9, #0xff00
-; GISEL-NEXT: orr w10, w11, w10
-; GISEL-NEXT: orr w8, w9, w8
-; GISEL-NEXT: orr w0, w10, w8
-; GISEL-NEXT: ret
+; CHECK-SD-LABEL: test_rev16_w:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: rev16 w0, w0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_rev16_w:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: lsr w8, w0, #8
+; CHECK-GI-NEXT: lsl w9, w0, #8
+; CHECK-GI-NEXT: and w10, w8, #0xff0000
+; CHECK-GI-NEXT: and w11, w9, #0xff000000
+; CHECK-GI-NEXT: and w8, w8, #0xff
+; CHECK-GI-NEXT: and w9, w9, #0xff00
+; CHECK-GI-NEXT: orr w10, w11, w10
+; CHECK-GI-NEXT: orr w8, w9, w8
+; CHECK-GI-NEXT: orr w0, w10, w8
+; CHECK-GI-NEXT: ret
entry:
%tmp1 = lshr i32 %X, 8
%X15 = bitcast i32 %X to i32
@@ -212,12 +193,6 @@ define i64 @test_rev16_x(i64 %a) nounwind {
; CHECK-NEXT: rev x8, x0
; CHECK-NEXT: ror x0, x8, #16
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test_rev16_x:
-; GISEL: // %bb.0: // %entry
-; GISEL-NEXT: rev x8, x0
-; GISEL-NEXT: ror x0, x8, #16
-; GISEL-NEXT: ret
entry:
%0 = tail call i64 @llvm.bswap.i64(i64 %a)
%1 = lshr i64 %0, 16
@@ -231,11 +206,6 @@ define i64 @test_rev32_x(i64 %a) nounwind {
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: rev32 x0, x0
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test_rev32_x:
-; GISEL: // %bb.0: // %entry
-; GISEL-NEXT: rev32 x0, x0
-; GISEL-NEXT: ret
entry:
%0 = tail call i64 @llvm.bswap.i64(i64 %a)
%1 = lshr i64 %0, 32
@@ -250,12 +220,6 @@ define <8 x i8> @test_vrev64D8(ptr %A) nounwind {
; CHECK-NEXT: ldr d0, [x0]
; CHECK-NEXT: rev64.8b v0, v0
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test_vrev64D8:
-; GISEL: // %bb.0:
-; GISEL-NEXT: ldr d0, [x0]
-; GISEL-NEXT: rev64.8b v0, v0
-; GISEL-NEXT: ret
%tmp1 = load <8 x i8>, ptr %A
%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
ret <8 x i8> %tmp2
@@ -267,12 +231,6 @@ define <4 x i16> @test_vrev64D16(ptr %A) nounwind {
; CHECK-NEXT: ldr d0, [x0]
; CHECK-NEXT: rev64.4h v0, v0
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test_vrev64D16:
-; GISEL: // %bb.0:
-; GISEL-NEXT: ldr d0, [x0]
-; GISEL-NEXT: rev64.4h v0, v0
-; GISEL-NEXT: ret
%tmp1 = load <4 x i16>, ptr %A
%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
ret <4 x i16> %tmp2
@@ -284,12 +242,6 @@ define <2 x i32> @test_vrev64D32(ptr %A) nounwind {
; CHECK-NEXT: ldr d0, [x0]
; CHECK-NEXT: rev64.2s v0, v0
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test_vrev64D32:
-; GISEL: // %bb.0:
-; GISEL-NEXT: ldr d0, [x0]
-; GISEL-NEXT: rev64.2s v0, v0
-; GISEL-NEXT: ret
%tmp1 = load <2 x i32>, ptr %A
%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> <i32 1, i32 0>
ret <2 x i32> %tmp2
@@ -301,12 +253,6 @@ define <2 x float> @test_vrev64Df(ptr %A) nounwind {
; CHECK-NEXT: ldr d0, [x0]
; CHECK-NEXT: rev64.2s v0, v0
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test_vrev64Df:
-; GISEL: // %bb.0:
-; GISEL-NEXT: ldr d0, [x0]
-; GISEL-NEXT: rev64.2s v0, v0
-; GISEL-NEXT: ret
%tmp1 = load <2 x float>, ptr %A
%tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> <i32 1, i32 0>
ret <2 x float> %tmp2
@@ -318,12 +264,6 @@ define <16 x i8> @test_vrev64Q8(ptr %A) nounwind {
; CHECK-NEXT: ldr q0, [x0]
; CHECK-NEXT: rev64.16b v0, v0
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test_vrev64Q8:
-; GISEL: // %bb.0:
-; GISEL-NEXT: ldr q0, [x0]
-; GISEL-NEXT: rev64.16b v0, v0
-; GISEL-NEXT: ret
%tmp1 = load <16 x i8>, ptr %A
%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>
ret <16 x i8> %tmp2
@@ -335,12 +275,6 @@ define <8 x i16> @test_vrev64Q16(ptr %A) nounwind {
; CHECK-NEXT: ldr q0, [x0]
; CHECK-NEXT: rev64.8h v0, v0
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test_vrev64Q16:
-; GISEL: // %bb.0:
-; GISEL-NEXT: ldr q0, [x0]
-; GISEL-NEXT: rev64.8h v0, v0
-; GISEL-NEXT: ret
%tmp1 = load <8 x i16>, ptr %A
%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
ret <8 x i16> %tmp2
@@ -352,12 +286,6 @@ define <4 x i32> @test_vrev64Q32(ptr %A) nounwind {
; CHECK-NEXT: ldr q0, [x0]
; CHECK-NEXT: rev64.4s v0, v0
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test_vrev64Q32:
-; GISEL: // %bb.0:
-; GISEL-NEXT: ldr q0, [x0]
-; GISEL-NEXT: rev64.4s v0, v0
-; GISEL-NEXT: ret
%tmp1 = load <4 x i32>, ptr %A
%tmp2 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
ret <4 x i32> %tmp2
@@ -369,12 +297,6 @@ define <4 x float> @test_vrev64Qf(ptr %A) nounwind {
; CHECK-NEXT: ldr q0, [x0]
; CHECK-NEXT: rev64.4s v0, v0
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test_vrev64Qf:
-; GISEL: // %bb.0:
-; GISEL-NEXT: ldr q0, [x0]
-; GISEL-NEXT: rev64.4s v0, v0
-; GISEL-NEXT: ret
%tmp1 = load <4 x float>, ptr %A
%tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
ret <4 x float> %tmp2
@@ -386,12 +308,6 @@ define <8 x i8> @test_vrev32D8(ptr %A) nounwind {
; CHECK-NEXT: ldr d0, [x0]
; CHECK-NEXT: rev32.8b v0, v0
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test_vrev32D8:
-; GISEL: // %bb.0:
-; GISEL-NEXT: ldr d0, [x0]
-; GISEL-NEXT: rev32.8b v0, v0
-; GISEL-NEXT: ret
%tmp1 = load <8 x i8>, ptr %A
%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
ret <8 x i8> %tmp2
@@ -403,50 +319,44 @@ define <4 x i16> @test_vrev32D16(ptr %A) nounwind {
; CHECK-NEXT: ldr d0, [x0]
; CHECK-NEXT: rev32.4h v0, v0
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test_vrev32D16:
-; GISEL: // %bb.0:
-; GISEL-NEXT: ldr d0, [x0]
-; GISEL-NEXT: rev32.4h v0, v0
-; GISEL-NEXT: ret
%tmp1 = load <4 x i16>, ptr %A
%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
ret <4 x i16> %tmp2
}
define <16 x i8> @test_vrev32Q8(ptr %A) nounwind {
-; CHECK-LABEL: test_vrev32Q8:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr q0, [x0]
-; CHECK-NEXT: rev32.16b v0, v0
-; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test_vrev32Q8:
-; GISEL: // %bb.0:
-; GISEL-NEXT: adrp x8, .LCPI21_0
-; GISEL-NEXT: ldr q0, [x0]
-; GISEL-NEXT: ldr q2, [x8, :lo12:.LCPI21_0]
-; GISEL-NEXT: tbl.16b v0, { v0, v1 }, v2
-; GISEL-NEXT: ret
+; CHECK-SD-LABEL: test_vrev32Q8:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr q0, [x0]
+; CHECK-SD-NEXT: rev32.16b v0, v0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vrev32Q8:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: adrp x8, .LCPI21_0
+; CHECK-GI-NEXT: ldr q0, [x0]
+; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI21_0]
+; CHECK-GI-NEXT: tbl.16b v0, { v0, v1 }, v2
+; CHECK-GI-NEXT: ret
%tmp1 = load <16 x i8>, ptr %A
%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12>
ret <16 x i8> %tmp2
}
define <8 x i16> @test_vrev32Q16(ptr %A) nounwind {
-; CHECK-LABEL: test_vrev32Q16:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr q0, [x0]
-; CHECK-NEXT: rev32.8h v0, v0
-; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test_vrev32Q16:
-; GISEL: // %bb.0:
-; GISEL-NEXT: adrp x8, .LCPI22_0
-; GISEL-NEXT: ldr q0, [x0]
-; GISEL-NEXT: ldr q2, [x8, :lo12:.LCPI22_0]
-; GISEL-NEXT: tbl.16b v0, { v0, v1 }, v2
-; GISEL-NEXT: ret
+; CHECK-SD-LABEL: test_vrev32Q16:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr q0, [x0]
+; CHECK-SD-NEXT: rev32.8h v0, v0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vrev32Q16:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: adrp x8, .LCPI22_0
+; CHECK-GI-NEXT: ldr q0, [x0]
+; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI22_0]
+; CHECK-GI-NEXT: tbl.16b v0, { v0, v1 }, v2
+; CHECK-GI-NEXT: ret
%tmp1 = load <8 x i16>, ptr %A
%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
ret <8 x i16> %tmp2
@@ -458,31 +368,25 @@ define <8 x i8> @test_vrev16D8(ptr %A) nounwind {
; CHECK-NEXT: ldr d0, [x0]
; CHECK-NEXT: rev16.8b v0, v0
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test_vrev16D8:
-; GISEL: // %bb.0:
-; GISEL-NEXT: ldr d0, [x0]
-; GISEL-NEXT: rev16.8b v0, v0
-; GISEL-NEXT: ret
%tmp1 = load <8 x i8>, ptr %A
%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
ret <8 x i8> %tmp2
}
define <16 x i8> @test_vrev16Q8(ptr %A) nounwind {
-; CHECK-LABEL: test_vrev16Q8:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr q0, [x0]
-; CHECK-NEXT: rev16.16b v0, v0
-; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test_vrev16Q8:
-; GISEL: // %bb.0:
-; GISEL-NEXT: adrp x8, .LCPI24_0
-; GISEL-NEXT: ldr q0, [x0]
-; GISEL-NEXT: ldr q2, [x8, :lo12:.LCPI24_0]
-; GISEL-NEXT: tbl.16b v0, { v0, v1 }, v2
-; GISEL-NEXT: ret
+; CHECK-SD-LABEL: test_vrev16Q8:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr q0, [x0]
+; CHECK-SD-NEXT: rev16.16b v0, v0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vrev16Q8:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: adrp x8, .LCPI24_0
+; CHECK-GI-NEXT: ldr q0, [x0]
+; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI24_0]
+; CHECK-GI-NEXT: tbl.16b v0, { v0, v1 }, v2
+; CHECK-GI-NEXT: ret
%tmp1 = load <16 x i8>, ptr %A
%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
ret <16 x i8> %tmp2
@@ -496,31 +400,25 @@ define <8 x i8> @test_vrev64D8_undef(ptr %A) nounwind {
; CHECK-NEXT: ldr d0, [x0]
; CHECK-NEXT: rev64.8b v0, v0
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test_vrev64D8_undef:
-; GISEL: // %bb.0:
-; GISEL-NEXT: ldr d0, [x0]
-; GISEL-NEXT: rev64.8b v0, v0
-; GISEL-NEXT: ret
%tmp1 = load <8 x i8>, ptr %A
%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 7, i32 undef, i32 undef, i32 4, i32 3, i32 2, i32 1, i32 0>
ret <8 x i8> %tmp2
}
define <8 x i16> @test_vrev32Q16_undef(ptr %A) nounwind {
-; CHECK-LABEL: test_vrev32Q16_undef:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr q0, [x0]
-; CHECK-NEXT: rev32.8h v0, v0
-; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test_vrev32Q16_undef:
-; GISEL: // %bb.0:
-; GISEL-NEXT: adrp x8, .LCPI26_0
-; GISEL-NEXT: ldr q0, [x0]
-; GISEL-NEXT: ldr q2, [x8, :lo12:.LCPI26_0]
-; GISEL-NEXT: tbl.16b v0, { v0, v1 }, v2
-; GISEL-NEXT: ret
+; CHECK-SD-LABEL: test_vrev32Q16_undef:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr q0, [x0]
+; CHECK-SD-NEXT: rev32.8h v0, v0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vrev32Q16_undef:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: adrp x8, .LCPI26_0
+; CHECK-GI-NEXT: ldr q0, [x0]
+; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI26_0]
+; CHECK-GI-NEXT: tbl.16b v0, { v0, v1 }, v2
+; CHECK-GI-NEXT: ret
%tmp1 = load <8 x i16>, ptr %A
%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 undef, i32 0, i32 undef, i32 2, i32 5, i32 4, i32 7, i32 undef>
ret <8 x i16> %tmp2
@@ -528,21 +426,21 @@ define <8 x i16> @test_vrev32Q16_undef(ptr %A) nounwind {
; vrev <4 x i16> should use REV32 and not REV64
define void @test_vrev64(ptr nocapture %source, ptr nocapture %dst) nounwind ssp {
-; CHECK-LABEL: test_vrev64:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: add x8, x1, #2
-; CHECK-NEXT: ldr q0, [x0]
-; CHECK-NEXT: st1.h { v0 }[5], [x8]
-; CHECK-NEXT: st1.h { v0 }[6], [x1]
-; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test_vrev64:
-; GISEL: // %bb.0: // %entry
-; GISEL-NEXT: add x8, x1, #2
-; GISEL-NEXT: ldr q0, [x0]
-; GISEL-NEXT: st1.h { v0 }[6], [x1]
-; GISEL-NEXT: st1.h { v0 }[5], [x8]
-; GISEL-NEXT: ret
+; CHECK-SD-LABEL: test_vrev64:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: add x8, x1, #2
+; CHECK-SD-NEXT: ldr q0, [x0]
+; CHECK-SD-NEXT: st1.h { v0 }[5], [x8]
+; CHECK-SD-NEXT: st1.h { v0 }[6], [x1]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vrev64:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: add x8, x1, #2
+; CHECK-GI-NEXT: ldr q0, [x0]
+; CHECK-GI-NEXT: st1.h { v0 }[6], [x1]
+; CHECK-GI-NEXT: st1.h { v0 }[5], [x8]
+; CHECK-GI-NEXT: ret
entry:
%tmp2 = load <8 x i16>, ptr %source, align 4
%tmp3 = extractelement <8 x i16> %tmp2, i32 6
@@ -555,24 +453,24 @@ entry:
; Test vrev of float4
define void @float_vrev64(ptr nocapture %source, ptr nocapture %dest) nounwind noinline ssp {
-; CHECK-LABEL: float_vrev64:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: movi.2d v0, #0000000000000000
-; CHECK-NEXT: add x8, x0, #12
-; CHECK-NEXT: dup.4s v0, v0[0]
-; CHECK-NEXT: ld1.s { v0 }[1], [x8]
-; CHECK-NEXT: str q0, [x1, #176]
-; CHECK-NEXT: ret
-;
-; GISEL-LABEL: float_vrev64:
-; GISEL: // %bb.0: // %entry
-; GISEL-NEXT: adrp x8, .LCPI28_0
-; GISEL-NEXT: movi d0, #0000000000000000
-; GISEL-NEXT: ldr q1, [x0]
-; GISEL-NEXT: ldr q2, [x8, :lo12:.LCPI28_0]
-; GISEL-NEXT: tbl.16b v0, { v0, v1 }, v2
-; GISEL-NEXT: str q0, [x1, #176]
-; GISEL-NEXT: ret
+; CHECK-SD-LABEL: float_vrev64:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: movi.2d v0, #0000000000000000
+; CHECK-SD-NEXT: add x8, x0, #12
+; CHECK-SD-NEXT: dup.4s v0, v0[0]
+; CHECK-SD-NEXT: ld1.s { v0 }[1], [x8]
+; CHECK-SD-NEXT: str q0, [x1, #176]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: float_vrev64:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: adrp x8, .LCPI28_0
+; CHECK-GI-NEXT: movi d0, #0000000000000000
+; CHECK-GI-NEXT: ldr q1, [x0]
+; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI28_0]
+; CHECK-GI-NEXT: tbl.16b v0, { v0, v1 }, v2
+; CHECK-GI-NEXT: str q0, [x1, #176]
+; CHECK-GI-NEXT: ret
entry:
%tmp2 = load <4 x float>, ptr %source, align 4
%tmp5 = shufflevector <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <4 x float> %tmp2, <4 x i32> <i32 0, i32 7, i32 0, i32 0>
@@ -587,11 +485,6 @@ define <4 x i32> @test_vrev32_bswap(<4 x i32> %source) nounwind {
; CHECK: // %bb.0:
; CHECK-NEXT: rev32.16b v0, v0
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test_vrev32_bswap:
-; GISEL: // %bb.0:
-; GISEL-NEXT: rev32.16b v0, v0
-; GISEL-NEXT: ret
%bswap = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %source)
ret <4 x i32> %bswap
}
@@ -600,30 +493,30 @@ declare <4 x i32> @llvm.bswap.v4i32(<4 x i32>) nounwind readnone
; Reduced regression from D114354
define void @test_rev16_truncstore() {
-; CHECK-LABEL: test_rev16_truncstore:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: cbnz wzr, .LBB30_2
-; CHECK-NEXT: .LBB30_1: // %cleanup
-; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: ldrh w8, [x8]
-; CHECK-NEXT: rev16 w8, w8
-; CHECK-NEXT: strh w8, [x8]
-; CHECK-NEXT: cbz wzr, .LBB30_1
-; CHECK-NEXT: .LBB30_2: // %fail
-; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test_rev16_truncstore:
-; GISEL: // %bb.0: // %entry
-; GISEL-NEXT: tbnz wzr, #0, .LBB30_2
-; GISEL-NEXT: .LBB30_1: // %cleanup
-; GISEL-NEXT: // =>This Inner Loop Header: Depth=1
-; GISEL-NEXT: ldrh w8, [x8]
-; GISEL-NEXT: rev w8, w8
-; GISEL-NEXT: lsr w8, w8, #16
-; GISEL-NEXT: strh w8, [x8]
-; GISEL-NEXT: tbz wzr, #0, .LBB30_1
-; GISEL-NEXT: .LBB30_2: // %fail
-; GISEL-NEXT: ret
+; CHECK-SD-LABEL: test_rev16_truncstore:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: cbnz wzr, .LBB30_2
+; CHECK-SD-NEXT: .LBB30_1: // %cleanup
+; CHECK-SD-NEXT: // =>This Inner Loop Header: Depth=1
+; CHECK-SD-NEXT: ldrh w8, [x8]
+; CHECK-SD-NEXT: rev16 w8, w8
+; CHECK-SD-NEXT: strh w8, [x8]
+; CHECK-SD-NEXT: cbz wzr, .LBB30_1
+; CHECK-SD-NEXT: .LBB30_2: // %fail
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_rev16_truncstore:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: tbnz wzr, #0, .LBB30_2
+; CHECK-GI-NEXT: .LBB30_1: // %cleanup
+; CHECK-GI-NEXT: // =>This Inner Loop Header: Depth=1
+; CHECK-GI-NEXT: ldrh w8, [x8]
+; CHECK-GI-NEXT: rev w8, w8
+; CHECK-GI-NEXT: lsr w8, w8, #16
+; CHECK-GI-NEXT: strh w8, [x8]
+; CHECK-GI-NEXT: tbz wzr, #0, .LBB30_1
+; CHECK-GI-NEXT: .LBB30_2: // %fail
+; CHECK-GI-NEXT: ret
entry:
br label %body
@@ -645,28 +538,28 @@ declare i16 @llvm.bswap.i16(i16)
; Reduced regression from D120192
define void @test_bswap32_narrow(ptr %p0, ptr %p1) nounwind {
-; CHECK-LABEL: test_bswap32_narrow:
-; CHECK: // %bb.0:
-; CHECK-NEXT: stp x30, x19, [sp, #-16]! // 16-byte Folded Spill
-; CHECK-NEXT: ldrh w8, [x0, #2]
-; CHECK-NEXT: mov x19, x1
-; CHECK-NEXT: rev16 w0, w8
-; CHECK-NEXT: bl gid_tbl_len
-; CHECK-NEXT: strh wzr, [x19]
-; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload
-; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test_bswap32_narrow:
-; GISEL: // %bb.0:
-; GISEL-NEXT: stp x30, x19, [sp, #-16]! // 16-byte Folded Spill
-; GISEL-NEXT: ldr w8, [x0]
-; GISEL-NEXT: mov x19, x1
-; GISEL-NEXT: and w8, w8, #0xffff0000
-; GISEL-NEXT: rev w0, w8
-; GISEL-NEXT: bl gid_tbl_len
-; GISEL-NEXT: strh wzr, [x19]
-; GISEL-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload
-; GISEL-NEXT: ret
+; CHECK-SD-LABEL: test_bswap32_narrow:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: stp x30, x19, [sp, #-16]! // 16-byte Folded Spill
+; CHECK-SD-NEXT: ldrh w8, [x0, #2]
+; CHECK-SD-NEXT: mov x19, x1
+; CHECK-SD-NEXT: rev16 w0, w8
+; CHECK-SD-NEXT: bl gid_tbl_len
+; CHECK-SD-NEXT: strh wzr, [x19]
+; CHECK-SD-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_bswap32_narrow:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: stp x30, x19, [sp, #-16]! // 16-byte Folded Spill
+; CHECK-GI-NEXT: ldr w8, [x0]
+; CHECK-GI-NEXT: mov x19, x1
+; CHECK-GI-NEXT: and w8, w8, #0xffff0000
+; CHECK-GI-NEXT: rev w0, w8
+; CHECK-GI-NEXT: bl gid_tbl_len
+; CHECK-GI-NEXT: strh wzr, [x19]
+; CHECK-GI-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload
+; CHECK-GI-NEXT: ret
%ld = load i32, ptr %p0, align 4
%and = and i32 %ld, -65536
%bswap = tail call i32 @llvm.bswap.i32(i32 %and)
@@ -686,11 +579,6 @@ define i64 @test_rev16_x_hwbyteswaps(i64 %a) nounwind {
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: rev16 x0, x0
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test_rev16_x_hwbyteswaps:
-; GISEL: // %bb.0: // %entry
-; GISEL-NEXT: rev16 x0, x0
-; GISEL-NEXT: ret
entry:
%0 = lshr i64 %a, 8
%1 = and i64 %0, 71777214294589695
@@ -702,45 +590,45 @@ entry:
; Optimize pattern with multiple and/or to a simple pattern which can enable generation of rev16.
define i64 @test_rev16_x_hwbyteswaps_complex1(i64 %a) nounwind {
-; CHECK-LABEL: test_rev16_x_hwbyteswaps_complex1:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: lsr x8, x0, #48
-; CHECK-NEXT: lsr x9, x0, #8
-; CHECK-NEXT: lsr x10, x0, #32
-; CHECK-NEXT: and x11, x9, #0xff000000000000
-; CHECK-NEXT: lsr x12, x0, #16
-; CHECK-NEXT: bfi x11, x8, #56, #8
-; CHECK-NEXT: and x8, x9, #0xff00000000
-; CHECK-NEXT: orr x8, x11, x8
-; CHECK-NEXT: and x9, x9, #0xff0000
-; CHECK-NEXT: bfi x8, x10, #40, #8
-; CHECK-NEXT: orr x8, x8, x9
-; CHECK-NEXT: ubfiz x9, x0, #8, #8
-; CHECK-NEXT: bfi x8, x12, #24, #8
-; CHECK-NEXT: bfxil x8, x0, #8, #8
-; CHECK-NEXT: orr x0, x8, x9
-; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test_rev16_x_hwbyteswaps_complex1:
-; GISEL: // %bb.0: // %entry
-; GISEL-NEXT: lsr x8, x0, #8
-; GISEL-NEXT: lsl x9, x0, #8
-; GISEL-NEXT: and x10, x8, #0xff000000000000
-; GISEL-NEXT: and x11, x9, #0xff00000000000000
-; GISEL-NEXT: and x12, x8, #0xff00000000
-; GISEL-NEXT: and x13, x9, #0xff0000000000
-; GISEL-NEXT: orr x10, x10, x11
-; GISEL-NEXT: orr x11, x12, x13
-; GISEL-NEXT: and x12, x8, #0xff0000
-; GISEL-NEXT: and x13, x9, #0xff000000
-; GISEL-NEXT: orr x12, x12, x13
-; GISEL-NEXT: and x8, x8, #0xff
-; GISEL-NEXT: orr x10, x10, x11
-; GISEL-NEXT: orr x8, x12, x8
-; GISEL-NEXT: orr x8, x10, x8
-; GISEL-NEXT: and x9, x9, #0xff00
-; GISEL-NEXT: orr x0, x8, x9
-; GISEL-NEXT: ret
+; CHECK-SD-LABEL: test_rev16_x_hwbyteswaps_complex1:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: lsr x8, x0, #48
+; CHECK-SD-NEXT: lsr x9, x0, #8
+; CHECK-SD-NEXT: lsr x10, x0, #32
+; CHECK-SD-NEXT: and x11, x9, #0xff000000000000
+; CHECK-SD-NEXT: lsr x12, x0, #16
+; CHECK-SD-NEXT: bfi x11, x8, #56, #8
+; CHECK-SD-NEXT: and x8, x9, #0xff00000000
+; CHECK-SD-NEXT: orr x8, x11, x8
+; CHECK-SD-NEXT: and x9, x9, #0xff0000
+; CHECK-SD-NEXT: bfi x8, x10, #40, #8
+; CHECK-SD-NEXT: orr x8, x8, x9
+; CHECK-SD-NEXT: ubfiz x9, x0, #8, #8
+; CHECK-SD-NEXT: bfi x8, x12, #24, #8
+; CHECK-SD-NEXT: bfxil x8, x0, #8, #8
+; CHECK-SD-NEXT: orr x0, x8, x9
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_rev16_x_hwbyteswaps_complex1:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: lsr x8, x0, #8
+; CHECK-GI-NEXT: lsl x9, x0, #8
+; CHECK-GI-NEXT: and x10, x8, #0xff000000000000
+; CHECK-GI-NEXT: and x11, x9, #0xff00000000000000
+; CHECK-GI-NEXT: and x12, x8, #0xff00000000
+; CHECK-GI-NEXT: and x13, x9, #0xff0000000000
+; CHECK-GI-NEXT: orr x10, x10, x11
+; CHECK-GI-NEXT: orr x11, x12, x13
+; CHECK-GI-NEXT: and x12, x8, #0xff0000
+; CHECK-GI-NEXT: and x13, x9, #0xff000000
+; CHECK-GI-NEXT: orr x12, x12, x13
+; CHECK-GI-NEXT: and x8, x8, #0xff
+; CHECK-GI-NEXT: orr x10, x10, x11
+; CHECK-GI-NEXT: orr x8, x12, x8
+; CHECK-GI-NEXT: orr x8, x10, x8
+; CHECK-GI-NEXT: and x9, x9, #0xff00
+; CHECK-GI-NEXT: orr x0, x8, x9
+; CHECK-GI-NEXT: ret
entry:
%0 = lshr i64 %a, 8
%1 = and i64 %0, 71776119061217280
@@ -763,40 +651,40 @@ entry:
}
define i64 @test_rev16_x_hwbyteswaps_complex2(i64 %a) nounwind {
-; CHECK-LABEL: test_rev16_x_hwbyteswaps_complex2:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: lsr x9, x0, #48
-; CHECK-NEXT: lsr x10, x0, #32
-; CHECK-NEXT: lsr x8, x0, #8
-; CHECK-NEXT: lsr x11, x0, #16
-; CHECK-NEXT: and x8, x8, #0xff00ff00ff00ff
-; CHECK-NEXT: bfi x8, x9, #56, #8
-; CHECK-NEXT: bfi x8, x10, #40, #8
-; CHECK-NEXT: bfi x8, x11, #24, #8
-; CHECK-NEXT: bfi x8, x0, #8, #8
-; CHECK-NEXT: mov x0, x8
-; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test_rev16_x_hwbyteswaps_complex2:
-; GISEL: // %bb.0: // %entry
-; GISEL-NEXT: lsr x8, x0, #8
-; GISEL-NEXT: lsl x9, x0, #8
-; GISEL-NEXT: and x10, x8, #0xff000000000000
-; GISEL-NEXT: and x11, x8, #0xff00000000
-; GISEL-NEXT: and x12, x8, #0xff0000
-; GISEL-NEXT: and x8, x8, #0xff
-; GISEL-NEXT: orr x10, x10, x11
-; GISEL-NEXT: orr x8, x12, x8
-; GISEL-NEXT: and x11, x9, #0xff00000000000000
-; GISEL-NEXT: and x12, x9, #0xff0000000000
-; GISEL-NEXT: orr x11, x11, x12
-; GISEL-NEXT: and x12, x9, #0xff000000
-; GISEL-NEXT: orr x8, x10, x8
-; GISEL-NEXT: orr x10, x11, x12
-; GISEL-NEXT: orr x8, x8, x10
-; GISEL-NEXT: and x9, x9, #0xff00
-; GISEL-NEXT: orr x0, x8, x9
-; GISEL-NEXT: ret
+; CHECK-SD-LABEL: test_rev16_x_hwbyteswaps_complex2:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: lsr x9, x0, #48
+; CHECK-SD-NEXT: lsr x10, x0, #32
+; CHECK-SD-NEXT: lsr x8, x0, #8
+; CHECK-SD-NEXT: lsr x11, x0, #16
+; CHECK-SD-NEXT: and x8, x8, #0xff00ff00ff00ff
+; CHECK-SD-NEXT: bfi x8, x9, #56, #8
+; CHECK-SD-NEXT: bfi x8, x10, #40, #8
+; CHECK-SD-NEXT: bfi x8, x11, #24, #8
+; CHECK-SD-NEXT: bfi x8, x0, #8, #8
+; CHECK-SD-NEXT: mov x0, x8
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_rev16_x_hwbyteswaps_complex2:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: lsr x8, x0, #8
+; CHECK-GI-NEXT: lsl x9, x0, #8
+; CHECK-GI-NEXT: and x10, x8, #0xff000000000000
+; CHECK-GI-NEXT: and x11, x8, #0xff00000000
+; CHECK-GI-NEXT: and x12, x8, #0xff0000
+; CHECK-GI-NEXT: and x8, x8, #0xff
+; CHECK-GI-NEXT: orr x10, x10, x11
+; CHECK-GI-NEXT: orr x8, x12, x8
+; CHECK-GI-NEXT: and x11, x9, #0xff00000000000000
+; CHECK-GI-NEXT: and x12, x9, #0xff0000000000
+; CHECK-GI-NEXT: orr x11, x11, x12
+; CHECK-GI-NEXT: and x12, x9, #0xff000000
+; CHECK-GI-NEXT: orr x8, x10, x8
+; CHECK-GI-NEXT: orr x10, x11, x12
+; CHECK-GI-NEXT: orr x8, x8, x10
+; CHECK-GI-NEXT: and x9, x9, #0xff00
+; CHECK-GI-NEXT: orr x0, x8, x9
+; CHECK-GI-NEXT: ret
entry:
%0 = lshr i64 %a, 8
%1 = and i64 %0, 71776119061217280
@@ -820,45 +708,45 @@ entry:
; Optimize pattern with multiple and/or to a simple pattern which can enable generation of rev16.
define i64 @test_rev16_x_hwbyteswaps_complex3(i64 %a) nounwind {
-; CHECK-LABEL: test_rev16_x_hwbyteswaps_complex3:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: lsr x8, x0, #48
-; CHECK-NEXT: lsr x9, x0, #8
-; CHECK-NEXT: lsr x10, x0, #32
-; CHECK-NEXT: and x11, x9, #0xff000000000000
-; CHECK-NEXT: lsr x12, x0, #16
-; CHECK-NEXT: bfi x11, x8, #56, #8
-; CHECK-NEXT: and x8, x9, #0xff00000000
-; CHECK-NEXT: orr x8, x8, x11
-; CHECK-NEXT: and x9, x9, #0xff0000
-; CHECK-NEXT: bfi x8, x10, #40, #8
-; CHECK-NEXT: orr x8, x9, x8
-; CHECK-NEXT: ubfiz x9, x0, #8, #8
-; CHECK-NEXT: bfi x8, x12, #24, #8
-; CHECK-NEXT: bfxil x8, x0, #8, #8
-; CHECK-NEXT: orr x0, x9, x8
-; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test_rev16_x_hwbyteswaps_complex3:
-; GISEL: // %bb.0: // %entry
-; GISEL-NEXT: lsr x8, x0, #8
-; GISEL-NEXT: lsl x9, x0, #8
-; GISEL-NEXT: and x10, x8, #0xff000000000000
-; GISEL-NEXT: and x11, x9, #0xff00000000000000
-; GISEL-NEXT: and x12, x8, #0xff00000000
-; GISEL-NEXT: and x13, x9, #0xff0000000000
-; GISEL-NEXT: orr x10, x11, x10
-; GISEL-NEXT: orr x11, x13, x12
-; GISEL-NEXT: and x12, x8, #0xff0000
-; GISEL-NEXT: and x13, x9, #0xff000000
-; GISEL-NEXT: orr x12, x13, x12
-; GISEL-NEXT: and x8, x8, #0xff
-; GISEL-NEXT: orr x10, x11, x10
-; GISEL-NEXT: orr x8, x8, x12
-; GISEL-NEXT: orr x8, x8, x10
-; GISEL-NEXT: and x9, x9, #0xff00
-; GISEL-NEXT: orr x0, x9, x8
-; GISEL-NEXT: ret
+; CHECK-SD-LABEL: test_rev16_x_hwbyteswaps_complex3:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: lsr x8, x0, #48
+; CHECK-SD-NEXT: lsr x9, x0, #8
+; CHECK-SD-NEXT: lsr x10, x0, #32
+; CHECK-SD-NEXT: and x11, x9, #0xff000000000000
+; CHECK-SD-NEXT: lsr x12, x0, #16
+; CHECK-SD-NEXT: bfi x11, x8, #56, #8
+; CHECK-SD-NEXT: and x8, x9, #0xff00000000
+; CHECK-SD-NEXT: orr x8, x8, x11
+; CHECK-SD-NEXT: and x9, x9, #0xff0000
+; CHECK-SD-NEXT: bfi x8, x10, #40, #8
+; CHECK-SD-NEXT: orr x8, x9, x8
+; CHECK-SD-NEXT: ubfiz x9, x0, #8, #8
+; CHECK-SD-NEXT: bfi x8, x12, #24, #8
+; CHECK-SD-NEXT: bfxil x8, x0, #8, #8
+; CHECK-SD-NEXT: orr x0, x9, x8
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_rev16_x_hwbyteswaps_complex3:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: lsr x8, x0, #8
+; CHECK-GI-NEXT: lsl x9, x0, #8
+; CHECK-GI-NEXT: and x10, x8, #0xff000000000000
+; CHECK-GI-NEXT: and x11, x9, #0xff00000000000000
+; CHECK-GI-NEXT: and x12, x8, #0xff00000000
+; CHECK-GI-NEXT: and x13, x9, #0xff0000000000
+; CHECK-GI-NEXT: orr x10, x11, x10
+; CHECK-GI-NEXT: orr x11, x13, x12
+; CHECK-GI-NEXT: and x12, x8, #0xff0000
+; CHECK-GI-NEXT: and x13, x9, #0xff000000
+; CHECK-GI-NEXT: orr x12, x13, x12
+; CHECK-GI-NEXT: and x8, x8, #0xff
+; CHECK-GI-NEXT: orr x10, x11, x10
+; CHECK-GI-NEXT: orr x8, x8, x12
+; CHECK-GI-NEXT: orr x8, x8, x10
+; CHECK-GI-NEXT: and x9, x9, #0xff00
+; CHECK-GI-NEXT: orr x0, x9, x8
+; CHECK-GI-NEXT: ret
entry:
%0 = lshr i64 %a, 8
%1 = and i64 %0, 71776119061217280
@@ -881,26 +769,26 @@ entry:
}
define i64 @test_or_and_combine1(i64 %a) nounwind {
-; CHECK-LABEL: test_or_and_combine1:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: lsr x8, x0, #24
-; CHECK-NEXT: lsr x9, x0, #8
-; CHECK-NEXT: and x10, x9, #0xff000000000000
-; CHECK-NEXT: bfi x10, x8, #32, #8
-; CHECK-NEXT: and x8, x9, #0xff0000
-; CHECK-NEXT: orr x0, x10, x8
-; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test_or_and_combine1:
-; GISEL: // %bb.0: // %entry
-; GISEL-NEXT: lsr x8, x0, #8
-; GISEL-NEXT: lsl x9, x0, #8
-; GISEL-NEXT: and x10, x8, #0xff000000000000
-; GISEL-NEXT: and x9, x9, #0xff00000000
-; GISEL-NEXT: orr x9, x10, x9
-; GISEL-NEXT: and x8, x8, #0xff0000
-; GISEL-NEXT: orr x0, x9, x8
-; GISEL-NEXT: ret
+; CHECK-SD-LABEL: test_or_and_combine1:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: lsr x8, x0, #24
+; CHECK-SD-NEXT: lsr x9, x0, #8
+; CHECK-SD-NEXT: and x10, x9, #0xff000000000000
+; CHECK-SD-NEXT: bfi x10, x8, #32, #8
+; CHECK-SD-NEXT: and x8, x9, #0xff0000
+; CHECK-SD-NEXT: orr x0, x10, x8
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_or_and_combine1:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: lsr x8, x0, #8
+; CHECK-GI-NEXT: lsl x9, x0, #8
+; CHECK-GI-NEXT: and x10, x8, #0xff000000000000
+; CHECK-GI-NEXT: and x9, x9, #0xff00000000
+; CHECK-GI-NEXT: orr x9, x10, x9
+; CHECK-GI-NEXT: and x8, x8, #0xff0000
+; CHECK-GI-NEXT: orr x0, x9, x8
+; CHECK-GI-NEXT: ret
entry:
%0 = lshr i64 %a, 8
%1 = and i64 %0, 71776119061217280
@@ -924,18 +812,6 @@ define i64 @test_or_and_combine2(i64 %a, i64 %b) nounwind {
; CHECK-NEXT: orr x8, x11, x8
; CHECK-NEXT: orr x0, x9, x8
; CHECK-NEXT: ret
-;
-; GISEL-LABEL: test_or_and_combine2:
-; GISEL: // %bb.0: // %entry
-; GISEL-NEXT: lsr x8, x0, #8
-; GISEL-NEXT: lsl x9, x0, #8
-; GISEL-NEXT: and x10, x8, #0xff000000000000
-; GISEL-NEXT: and x11, x9, #0xff00000000
-; GISEL-NEXT: and x8, x8, #0xff0000
-; GISEL-NEXT: orr x9, x10, x9
-; GISEL-NEXT: orr x8, x11, x8
-; GISEL-NEXT: orr x0, x9, x8
-; GISEL-NEXT: ret
entry:
%0 = lshr i64 %a, 8
%1 = and i64 %0, 71776119061217280
@@ -949,19 +825,19 @@ entry:
}
define i32 @pr55484(i32 %0) {
-; CHECK-LABEL: pr55484:
-; CHECK: // %bb.0:
-; CHECK-NEXT: lsr w8, w0, #8
-; CHECK-NEXT: orr w8, w8, w0, lsl #8
-; CHECK-NEXT: sxth w0, w8
-; CHECK-NEXT: ret
-;
-; GISEL-LABEL: pr55484:
-; GISEL: // %bb.0:
-; GISEL-NEXT: lsl w8, w0, #8
-; GISEL-NEXT: orr w8, w8, w0, lsr #8
-; GISEL-NEXT: sxth w0, w8
-; GISEL-NEXT: ret
+; CHECK-SD-LABEL: pr55484:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: lsr w8, w0, #8
+; CHECK-SD-NEXT: orr w8, w8, w0, lsl #8
+; CHECK-SD-NEXT: sxth w0, w8
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: pr55484:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: lsl w8, w0, #8
+; CHECK-GI-NEXT: orr w8, w8, w0, lsr #8
+; CHECK-GI-NEXT: sxth w0, w8
+; CHECK-GI-NEXT: ret
%2 = lshr i32 %0, 8
%3 = shl i32 %0, 8
%4 = or i32 %2, %3
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