[PATCH] D156832: [GlobalISel] Handle trunc(sext x) in artifact combiner

[Vladislav Dzhidzhoev via Phabricator via llvm-commits]

dzhidzhoev updated this revision to Diff 546914.
dzhidzhoev added a comment.

Addressed @jroelofs and @arsenm comments.
Now we find sequences of trunc/sext/anyext/zext instructions, starting with trunc(...),
and replace the destination of trunc with the source of nested instructions if
the destination and "nested" source types are matching.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156832/new/

https://reviews.llvm.org/D156832

Files:
  llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
  llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-trunc.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz-zero-undef.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctpop.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz-zero-undef.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshl.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshr.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-rotl-rotr.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.mir

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