[PATCH] D156811: [InstCombine] Fold `select` of `srem` and conditional add

[Antonio Frighetto via Phabricator via llvm-commits]

antoniofrighetto added inline comments.


================
Comment at: llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp:2616
+        IC.isKnownToBeAPowerOfTwo(Remainder, /*OrZero*/ true) &&
+        FalseVal == RemRes))
+    return nullptr;
----------------
craig.topper wrote:
> goldstein.w.n wrote:
> > This needs to be `TrueIfSigned ? (FalseVal == Rem) : (TrueVal == Rem)`
> Wouldn't we need this right after we find the compare?
> 
> ```
> if (!TrueIfSigned)
>   std::swap(TrueVal, FalseVal)
> ```
As per `rem_euclid_2` test, I think that if we are handling a SGT, we should check that the `srem` is in the true arm. 


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  https://reviews.llvm.org/D156811/new/

https://reviews.llvm.org/D156811