[llvm] 4e814b1 - [TableGen][NFC] Refine obtaining qualified register class ids.

[Ivan Kosarev via llvm-commits]

Author: Ivan Kosarev
Date: 2023-08-03T11:07:57+01:00
New Revision: 4e814b10ecd60244b6061cfd8c9cba3136d1a38c

URL: https://github.com/llvm/llvm-project/commit/4e814b10ecd60244b6061cfd8c9cba3136d1a38c
DIFF: https://github.com/llvm/llvm-project/commit/4e814b10ecd60244b6061cfd8c9cba3136d1a38c.diff

LOG: [TableGen][NFC] Refine obtaining qualified register class ids.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D156110

Added: 
    

Modified: 
    llvm/utils/TableGen/CodeGenRegisters.cpp
    llvm/utils/TableGen/CodeGenRegisters.h
    llvm/utils/TableGen/DAGISelMatcherGen.cpp
    llvm/utils/TableGen/GlobalISelMatchTable.cpp
    llvm/utils/TableGen/RegisterBankEmitter.cpp
    llvm/utils/TableGen/RegisterInfoEmitter.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/utils/TableGen/CodeGenRegisters.cpp b/llvm/utils/TableGen/CodeGenRegisters.cpp
index 5c45290a06570e..74fb80610b9c17 100644
--- a/llvm/utils/TableGen/CodeGenRegisters.cpp
+++ b/llvm/utils/TableGen/CodeGenRegisters.cpp
@@ -965,11 +965,20 @@ static bool TopoOrderRC(const CodeGenRegisterClass &PA,
   return StringRef(A->getName()) < B->getName();
 }
 
+std::string CodeGenRegisterClass::getNamespaceQualification() const {
+  return Namespace.empty() ? "" : (Namespace + "::").str();
+}
+
 std::string CodeGenRegisterClass::getQualifiedName() const {
-  if (Namespace.empty())
-    return getName();
-  else
-    return (Namespace + "::" + getName()).str();
+  return getNamespaceQualification() + getName();
+}
+
+std::string CodeGenRegisterClass::getIdName() const {
+  return getName() + "RegClassID";
+}
+
+std::string CodeGenRegisterClass::getQualifiedIdName() const {
+  return getNamespaceQualification() + getIdName();
 }
 
 // Compute sub-classes of all register classes.

diff  --git a/llvm/utils/TableGen/CodeGenRegisters.h b/llvm/utils/TableGen/CodeGenRegisters.h
index 15f08d1431f9c0..6243f9dfd1eed4 100644
--- a/llvm/utils/TableGen/CodeGenRegisters.h
+++ b/llvm/utils/TableGen/CodeGenRegisters.h
@@ -353,8 +353,11 @@ namespace llvm {
     // created by TableGen.
     Record *getDef() const { return TheDef; }
 
+    std::string getNamespaceQualification() const;
     const std::string &getName() const { return Name; }
     std::string getQualifiedName() const;
+    std::string getIdName() const;
+    std::string getQualifiedIdName() const;
     ArrayRef<ValueTypeByHwMode> getValueTypes() const { return VTs; }
     unsigned getNumValueTypes() const { return VTs.size(); }
     bool hasType(const ValueTypeByHwMode &VT) const;

diff  --git a/llvm/utils/TableGen/DAGISelMatcherGen.cpp b/llvm/utils/TableGen/DAGISelMatcherGen.cpp
index f773f7c77a7713..d08f57b84b95f0 100644
--- a/llvm/utils/TableGen/DAGISelMatcherGen.cpp
+++ b/llvm/utils/TableGen/DAGISelMatcherGen.cpp
@@ -710,7 +710,7 @@ void MatcherGen::EmitResultLeafAsOperand(const TreePatternNode *N,
       const CodeGenRegisterClass &RC =
           CGP.getTargetInfo().getRegisterClass(Def);
       if (RC.EnumValue <= 127) {
-        std::string Value = getQualifiedName(Def) + "RegClassID";
+        std::string Value = RC.getQualifiedIdName();
         AddMatcher(new EmitStringIntegerMatcher(Value, MVT::i32));
         ResultOps.push_back(NextRecordedOperandNo++);
       } else {

diff  --git a/llvm/utils/TableGen/GlobalISelMatchTable.cpp b/llvm/utils/TableGen/GlobalISelMatchTable.cpp
index aab772f020a61c..bda4d4b7829fd8 100644
--- a/llvm/utils/TableGen/GlobalISelMatchTable.cpp
+++ b/llvm/utils/TableGen/GlobalISelMatchTable.cpp
@@ -1104,7 +1104,7 @@ void RegisterBankOperandMatcher::emitPredicateOpcodes(MatchTable &Table,
         << MatchTable::Comment("MI") << MatchTable::IntValue(InsnVarID)
         << MatchTable::Comment("Op") << MatchTable::IntValue(OpIdx)
         << MatchTable::Comment("RC")
-        << MatchTable::NamedValue(RC.getQualifiedName() + "RegClassID")
+        << MatchTable::NamedValue(RC.getQualifiedIdName())
         << MatchTable::LineBreak;
 }
 
@@ -2000,7 +2000,7 @@ void ConstrainOperandToRegClassAction::emitActionOpcodes(
   Table << MatchTable::Opcode("GIR_ConstrainOperandRC")
         << MatchTable::Comment("InsnID") << MatchTable::IntValue(InsnID)
         << MatchTable::Comment("Op") << MatchTable::IntValue(OpIdx)
-        << MatchTable::NamedValue(RC.getQualifiedName() + "RegClassID")
+        << MatchTable::NamedValue(RC.getQualifiedIdName())
         << MatchTable::LineBreak;
 }
 

diff  --git a/llvm/utils/TableGen/RegisterBankEmitter.cpp b/llvm/utils/TableGen/RegisterBankEmitter.cpp
index 2d23bf86b6ad84..60c3fcdba70ed8 100644
--- a/llvm/utils/TableGen/RegisterBankEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterBankEmitter.cpp
@@ -231,9 +231,7 @@ void RegisterBankEmitter::emitBaseClassImplementation(
     for (const auto &RCs : RCsGroupedByWord) {
       OS << "    // " << LowestIdxInWord << "-" << (LowestIdxInWord + 31) << "\n";
       for (const auto &RC : RCs) {
-        std::string QualifiedRegClassID =
-            (Twine(RC->Namespace) + "::" + RC->getName() + "RegClassID").str();
-        OS << "    (1u << (" << QualifiedRegClassID << " - "
+        OS << "    (1u << (" << RC->getQualifiedIdName() << " - "
            << LowestIdxInWord << ")) |\n";
       }
       OS << "    0,\n";

diff  --git a/llvm/utils/TableGen/RegisterInfoEmitter.cpp b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
index 7b1295382ee53d..7e537e07a5d234 100644
--- a/llvm/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
@@ -146,8 +146,7 @@ void RegisterInfoEmitter::runEnums(raw_ostream &OS,
       OS << "namespace " << Namespace << " {\n";
     OS << "enum {\n";
     for (const auto &RC : RegisterClasses)
-      OS << "  " << RC.getName() << "RegClassID"
-         << " = " << RC.EnumValue << ",\n";
+      OS << "  " << RC.getIdName() << " = " << RC.EnumValue << ",\n";
     OS << "\n};\n";
     if (!Namespace.empty())
       OS << "} // end namespace " << Namespace << "\n\n";
@@ -1072,8 +1071,8 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
       RegSize = RC.RSI.getSimple().RegSize;
     OS << "  { " << RCName << ", " << RCBitsName << ", "
        << RegClassStrings.get(RC.getName()) << ", " << RC.getOrder().size()
-       << ", " << RCBitsSize << ", " << RC.getQualifiedName() + "RegClassID"
-       << ", " << RegSize << ", " << RC.CopyCost << ", "
+       << ", " << RCBitsSize << ", " << RC.getQualifiedIdName() << ", "
+       << RegSize << ", " << RC.CopyCost << ", "
        << (RC.Allocatable ? "true" : "false") << " },\n";
   }
 
@@ -1621,8 +1620,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
         }
 
         OS << "    "
-           << (BaseRC ? BaseRC->getQualifiedName() + "RegClassID"
-                      : "InvalidRegClassID")
+           << (BaseRC ? BaseRC->getQualifiedIdName() : "InvalidRegClassID")
            << ",  // " << Reg.getName() << "\n";
       }
       OS << "  };\n\n"