[PATCH] D156972: [DAG] Fix crash in replaceStoreOfInsertLoad
Pierre van Houtryve via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 3 01:53:34 PDT 2023
Pierre-vh created this revision.
Pierre-vh added a reviewer: arsenm.
Herald added subscribers: kerbowa, hiraditya, jvesely.
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Herald added subscribers: llvm-commits, wdng.
Herald added a project: LLVM.
Idx's type can be different from Ptr's, causing a "Binary operator types must match" assertion failure when emitting the MUL.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D156972
Files:
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/test/CodeGen/AMDGPU/replace-store-of-insert-load.ll
Index: llvm/test/CodeGen/AMDGPU/replace-store-of-insert-load.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AMDGPU/replace-store-of-insert-load.ll
@@ -0,0 +1,19 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -march=amdgcn -mcpu=gfx90a -verify-machineinstrs < %s | FileCheck %s
+
+; Regression test for a bug in `DAGCombiner::replaceStoreOfInsertLoad` where
+; Idx could be smaller than PtrVT, causing a MUL to be emitted with inconsistent
+; LHS/RHS types.
+
+define void @main(ptr addrspace(1) %in, float %arg) {
+; CHECK-LABEL: main:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: global_store_dword v[0:1], v2, off offset:12
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+ %1 = load <4 x float>, ptr addrspace(1) %in
+ %2 = insertelement <4 x float> %1, float %arg, i64 3
+ store <4 x float> %2, ptr addrspace(1) %in
+ ret void
+}
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -20523,6 +20523,9 @@
return SDValue();
EVT PtrVT = Ptr.getValueType();
+ if(Idx.getValueType().getSizeInBits() < PtrVT.getSizeInBits())
+ Idx = DAG.getZExtOrTrunc(Idx, DL, PtrVT);
+
SDValue Offset =
DAG.getNode(ISD::MUL, DL, PtrVT, Idx,
DAG.getConstant(EltVT.getSizeInBits() / 8, DL, PtrVT));
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